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| this is information on a product in full production. december 2016 docid029656 rev 2 1/129 ST25R3911B high performance hf reader / nfc initiator with 1.4 w suppor ting vhbr and aat datasheet - production data features ? iso 18092 (nfcip-1) active p2p ? iso14443a, iso14443b and felica? ? supports vhbr (3.4 mbit/s picc to pcd framing, 6.8 mbit/s afe and pcd to picc framing) ? capacitive sensing - wake-up ? automatic antenna tuning system providing tuning of antenna lc tank ? automatic modulation index adjustment ? am and pm (i/q) demodulator channels with automatic selection ? dpo (dynamic power output) ? up to 1.4 w in case of differential output ? user selectable and automatic gain control ? transparent and stream modes to implement mifare? classic compliant or other custom protocols ? possibility of driving two antennas in single ended mode ? oscillator input capable of operating with 13.56 mhz or 27.12 mhz crystal with fast start-up ? 6 mbit/s spi with 96 bytes fifo ? wide supply voltage range from 2.4 v to 5.5 v ? wide temperature range: -40 c to 125 c ? qfn32, 5 mm x 5 mm package description the ST25R3911B is a highly integrated nfc initiator / hf reader ic, including the analog front end (afe) and a highly integrated data framing system for iso 18092 (nfcip-1) initiator, iso 18092 (nfcip-1) active target, iso 14443a and b reader (including high bit rates) and felica? reader. implementation of other standard and custom protocols like mifare? classic is possible using the afe and implementing framing in the external microcontroller (stream and transparent modes). the ST25R3911B is positioned perfectly for the infrastructure side of the nfc system, where users need optimal rf pe rformance and flexibility combined wit h low power. thanks to automatic antenna tuning (aat) technology, the device is optimized for applications with direct ly driven antennas. the ST25R3911B is alone in the domain of hf reader ics as it contains two differential low impedance (1 ohm) antenna drivers. the ST25R3911B includes several features that make it very suited for low power applications. it contains a low power capacitive sensor that can be used to detect the presence of a card without switching on the reader field. the presence of a card can also be detected by performing a measurement of amplitude or phase of signal on antenna lc tank, and comparing it to the stored reference. it also contains a low power rc oscillator and wake-up time r that can be used to wake up the system after a defined time period, and to check for the presence of a tag using one or more low power detection techniques (capacitive, phase or amplitude). the ST25R3911B is designed to operate from a wide (2.4 v to 5.5 v) power supply range; peripheral interface io pins support power supply range from 1.65 v to 5.5 v. wafer qfn32 www.st.com
contents ST25R3911B 2/129 docid029656 rev 2 contents 1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.3 phase and amplitude detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.4 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.5 capacitive sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.6 external field detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1.7 quartz crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1.8 power supply regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1.9 por and bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1.10 rc oscillator and wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1.11 iso-14443 and nfcip-1 framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1.12 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1.13 control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1.14 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.2.4 capacitive sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.2.5 wake-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.2.6 quartz crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.2.7 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.2.8 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.2.9 phase and amplitude detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.2.10 external field detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.2.11 power supply system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.2.12 communication with an external microcon troller . . . . . . . . . . . . . . . . . . 32 1.2.13 direct commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.2.14 start timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.2.15 test access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.2.16 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1.2.17 reader operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 docid029656 rev 2 3/129 ST25R3911B contents 5 1.2.18 felica? reader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 1.2.19 nfcip-1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 1.2.20 am modulation depth: definition and calib ration . . . . . . . . . . . . . . . . . . 63 1.2.21 antenna tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.2.22 stream mode and transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.3.1 io configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.3.2 io configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.3.3 operation control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.3.4 mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 1.3.5 bit rate definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 1.3.6 iso14443a and nfc 106kb/s settings register . . . . . . . . . . . . . . . . . . 80 1.3.7 iso14443b settings register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 1.3.8 iso14443b and felica settings register . . . . . . . . . . . . . . . . . . . . . . . 82 1.3.9 stream mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 1.3.10 auxiliary definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 1.3.11 receiver configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 1.3.12 receiver configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1.3.13 receiver configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.3.14 receiver configuration register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.3.15 mask receive timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 1.3.16 no-response timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 1.3.17 no-response timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 1.3.18 general purpose and no-response time r control register . . . . . . . . . 90 1.3.19 general purpose timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 1.3.20 general purpose timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 1.3.21 mask main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 1.3.22 mask timer and nfc interrupt register . . . . . . . . . . . . . . . . . . . . . . . . 92 1.3.23 mask error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . 93 1.3.24 main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 1.3.25 timer and nfc interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 1.3.26 error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . 95 1.3.27 fifo status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 1.3.28 fifo status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 1.3.29 collision display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 1.3.30 number of transmitted bytes register 1 . . . . . . . . . . . . . . . . . . . . . . . . 97 1.3.31 number of transmitted bytes register 2 . . . . . . . . . . . . . . . . . . . . . . . . 98 contents ST25R3911B 4/129 docid029656 rev 2 1.3.32 nfcip bit rate detection display register . . . . . . . . . . . . . . . . . . . . . . 98 1.3.33 a/d converter output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 1.3.34 antenna calibration control register . . . . . . . . . . . . . . . . . . . . . . . . . . 99 1.3.35 antenna calibration target register . . . . . . . . . . . . . . . . . . . . . . . . . . 100 1.3.36 antenna calibration display register . . . . . . . . . . . . . . . . . . . . . . . . . 100 1.3.37 am modulation depth control register . . . . . . . . . . . . . . . . . . . . . . . . 101 1.3.38 am modulation depth display register . . . . . . . . . . . . . . . . . . . . . . . . 101 1.3.39 rfo am modulated level definition regi ster . . . . . . . . . . . . . . . . . . . 102 1.3.40 rfo normal level definition register . . . . . . . . . . . . . . . . . . . . . . . . . 102 1.3.41 external field detector threshold register . . . . . . . . . . . . . . . . . . . . . 103 1.3.42 regulator voltage control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 1.3.43 regulator and timer display register . . . . . . . . . . . . . . . . . . . . . . . . . 105 1.3.44 rssi display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 1.3.45 gain reduction state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 1.3.46 capacitive sensor control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 1.3.47 capacitive sensor display register . . . . . . . . . . . . . . . . . . . . . . . . . . 108 1.3.48 auxiliary display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 1.3.49 wake-up timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 1.3.50 amplitude measurement configuration register . . . . . . . . . . . . . . . . . 110 1.3.51 amplitude measurement reference register . . . . . . . . . . . . . . . . . . . 110 1.3.52 amplitude measurement auto-averaging display register . . . . . . . . . 111 1.3.53 amplitude measurement display register . . . . . . . . . . . . . . . . . . . . . . 111 1.3.54 phase measurement configuration register . . . . . . . . . . . . . . . . . . . . 112 1.3.55 phase measurement reference register . . . . . . . . . . . . . . . . . . . . . . 112 1.3.56 phase measurement auto-averaging display register . . . . . . . . . . . . 113 1.3.57 phase measurement display register . . . . . . . . . . . . . . . . . . . . . . . . 113 1.3.58 capacitance measurement configuration register . . . . . . . . . . . . . . . 114 1.3.59 capacitance measurement reference register . . . . . . . . . . . . . . . . . 114 1.3.60 capacitance measurement auto-averagi ng display register . . . . . . . 115 1.3.61 capacitance measurement display register . . . . . . . . . . . . . . . . . . . . 115 1.3.62 ic identity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 3 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 3.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 docid029656 rev 2 5/129 ST25R3911B contents 5 3.3 dc/ac characteristics for digital inputs and outputs . . . . . . . . . . . . . . . 120 3.3.1 cmos inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.3.2 cmos outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 3.5 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 3.5.1 thermal resistance and maximum power dissipation . . . . . . . . . . . . . 123 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.1 qfn32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 list of tables ST25R3911B 6/129 docid029656 rev 2 list of tables table 1. first and third stage zero setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 2. low pass control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 3. receiver filter selection and gain range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4. recommended blocking capacitor values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5. serial data interface (4-wire interface) signal lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 6. spi operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7. spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 8. irq output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 9. direct commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 10. timing parameters of nfc field on commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 11. register preset bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 12. analog test and observation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 13. test access register - tana signal selection of csi and cso pins. . . . . . . . . . . . . . . . . . 51 table 14. operation mode/bit rate setting for nfcip-1 pa ssive communication . . . . . . . . . . . . . . . . 59 table 15. operation mode/bit rate setting for nfcip-1 ac tive communication initiator . . . . . . . . . . . 60 table 16. setting mod bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 17. registers map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 18. io configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 19. io configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 20. operation control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 21. mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 22. initiator operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 23. target operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 24. bit rate definition register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 25. bit rate coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 26. iso14443a and nfc 106kb/s settings register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 27. iso14443a modulation pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 table 28. iso14443b settings register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 29. iso14443b and felica settings register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 30. minimum tr1 codings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 31. stream mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 32. sub-carrier frequ ency definition for sub-carrier and bpsk stream mode . . . . . . . . . . . . . 83 table 33. definition of time period for stream mode tx mo dulator control . . . . . . . . . . . . . . . . . . . . 83 table 34. auxiliary definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 35. receiver configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 36. receiver configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 37. receiver configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 38. receiver configuration register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 39. mask receive timer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 40. no-response timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 41. no-response timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 42. general purpose and no-response timer control r egister . . . . . . . . . . . . . . . . . . . . . . . 90 table 43. timer trigger source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 44. general purpose timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 45. general purpose timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 46. mask main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 47. mask timer and nfc interrupt regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 48. mask error and wake-up interrupt register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 docid029656 rev 2 7/129 ST25R3911B list of tables 8 table 49. main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 50. timer and nfc interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 51. error and wake-up interrupt regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 table 52. fifo status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 53. fifo status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 54. collision display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 55. number of transmitted bytes register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 56. number of transmitted bytes register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 57. nfcip bit rate detection display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 58. a/d converter output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 59. antenna calibration control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 60. antenna calibration target register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 0 table 61. antenna calibration display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 0 table 62. am modulation depth control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 63. am modulation depth display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 64. rfo am modulated level definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 65. rfo normal level definition regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 66. external field detector threshold register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 67. peer detection threshold as seen on rfi1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 68. collision avoidance thre shold as seen on rfi1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 69. regulator voltage control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 table 70. regulator and timer display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 71. regulated voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 72. rssi display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 73. rssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 74. gain reduction state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 75. capacitive sensor control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 07 table 76. capacitive sensor display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 table 77. auxiliary display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 78. wake-up timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 09 table 79. typical wake-up time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 80. amplitude measurement configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 81. amplitude measurement reference register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 82. amplitude measurement auto-averaging display register . . . . . . . . . . . . . . . . . . . . . . . 111 table 83. amplitude measurement display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 84. phase measurement configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 85. phase measurement reference register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 86. phase measurement auto-averaging display regist er . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 87. phase measurement display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 88. capacitance measurement configur ation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 89. capacitance measurement reference register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 90. capacitance measurement auto -averaging display register . . . . . . . . . . . . . . . . . . . . . 115 table 91. capacitance measurement display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 92. ic identity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 93. ST25R3911B pin definitions - qfn32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 94. electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 95. electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 96. temperature ranges and storage conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 97. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 98. cmos inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 99. cmos outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 100. electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 list of tables ST25R3911B 8/129 docid029656 rev 2 table 101. qfn32 5 mm x 5 mm dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 102. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 103. ordering information scheme (unsawn wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 104. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 docid029656 rev 2 9/129 ST25R3911B list of figures 9 list of figures figure 1. ST25R3911B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. minimum configuration with single sided antenna driving (including emc filter) . . . . . . . . 14 figure 3. minimum configuration with di fferential antenna driving (including emc filter). . . . . . . . . . 14 figure 4. receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. capacitive sensor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 6. phase detector inputs and output in case of 90o phase shift . . . . . . . . . . . . . . . . . . . . . . . 28 figure 7. phase detector inputs and output in case of 135o phase shift . . . . . . . . . . . . . . . . . . . . . . 28 figure 8. ST25R3911B power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9. exchange of signals with microcontr oller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 figure 10. spi communication: writing a single byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 figure 11. spi communication: writing mult iple bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 12. spi communication: reading a single byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 13. spi communication: loading of fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 14. spi communication: reading of fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 15. spi communication: direct command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 16. spi communication: direct command chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 17. spi general timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 18. spi read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 19. direct command nfc initial field on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 20. direct command nfc response field on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 21. iso14443a states for pcd and picc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 22. selection of mrt and nrt for a given fdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 23. flowchart for iso14443a antic ollision with ST25R3911B . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 24. felica? frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 25. transport frame format accordi ng to nfcip-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 26. connection of tuning capacitors to the antenna lc tank . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 27. example of sub-carrier stream mode for scf = 01b and scp = 10b . . . . . . . . . . . . . . . . . . . 70 figure 28. example of bpsk stream mode for scf = 01b an d scp = 10b. . . . . . . . . . . . . . . . . . . . . . . 71 figure 29. example of tx in stream mode for stx = 00 0b and ook modulation . . . . . . . . . . . . . . . . . 71 figure 30. ST25R3911B qfn32 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 31. tcase vs. power with different copper area at tamb = 25c . . . . . . . . . . . . . . . . . . . . . 123 figure 32. rthca vs. copper area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 33. qfn32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 functional overview ST25R3911B 10/129 docid029656 rev 2 1 functional overview the ST25R3911B is suitable for a wide range of applications, among them ? emv payment ? e-government ? access control ? nfc infrastructure ? ticketing 1.1 block diagram the block diagram is shown in figure 1 . figure 1. ST25R3911B block diagram 6 7 5 % 0 6 9 / r j l f ; 7 2 ; 7 , 5 ) 2 5 ) , 5 ) , 6 3 , 9 ' ' & 6 , & 6 2 9 ' ' b , 2 5 ) 2 , 5 4 0 & 8 b & / . 7 5 , 0 [ 5 h f h l y h u 7 u d q v p l w w h u 5 h j x o d w r u v $ ' f r q y h u w h u ; 7 $ / r v f l o o d w r u 3 2 5 d q g % l d v ( [ w h u q d o i l h o g g h w h f w r u & d s d f l w l y h v h q v r u 5 & r v f l o o d w r u / h y h o v k l i w h u v 3 k d v h d q g d p s o l w x g h g h w h f w r u ) , ) 2 & r q w u r o o r j l f 6 3 , ) u d p l q j : d n h 8 s w l p h u docid029656 rev 2 11/129 ST25R3911B functional overview 71 1.1.1 transmitter the transmitter incorporates drivers that dr ive external antenna through pins rfo1 and rfo2. single sided and differential driving is possible. the transmitter block additionally contains a sub-block that modulates transmitted signal (ook or configurable am modulation). the ST25R3911B transmitter is intended to directly drive antennas (without 50 ? cable, usually antenna is on the same pcb). operation with 50 ? cable is also possible, but in that case some of the advanced features are not available. 1.1.2 receiver the receiver detects transponder modulatio n superimposed on the 13.56 mhz carrier signal. the receiver contains two receiv e chains (one for am and another for pm demodulation) composed of a peak detector followed by two gain and filtering stages and a final digitizer stage. the filter characteristi cs are adjusted to optimize performance for each mode and bit rate (sub-carrier frequencies from 212 khz to 6.8 mhz are supported). the receiver chain inputs are the rfi1 and rfi2 pins. the receiver chain incorporates several features that enable reliable operation in challenging phase and noise conditions. 1.1.3 phase and am plitude detector the phase detector is observing the phase diff erence between the transmitter output signals (rfo1 and rfo2) and the receiver input signals (rfi1 and rfi2). the amplitude detector is observing the amplitude of the receiver input signals (rfi1 and rfi2) via self-mixing. the amplitude of the receiver input signals (rfi 1 and rfi2) is directly proportional to the amplitude of the antenna lc tank signal. the phase detector and the amplitude detector can be used for the following purposes: ? pm demodulation by observing rfi1 and rfi2 phase variation ? average phase difference between rfox pins and rfix pins is used to check and optimize antenna tuning ? amplitude of signal present on rfi1 and rfi2 pins is used to check and optimize antenna tuning 1.1.4 a/d converter the ST25R3911B contains a built in analog to digital (a/d) converter. its input can be multiplexed from different sources and is used in several applications (measurement of rf amplitude and phase, calibration of modulation depth?). the result of the a/d conversion is stored in the a/d converter output register and can be read via spi. 1.1.5 capacitive sensor the capacitive sensor is used to implement lo w power detection of transponder presence, it measures the capacitance between two copp er patches connected to the csi and cso pins. the capacitance changes with the pres ence of an object (card, hand). during calibration the reference capacitance (repr esenting parasitic capacitance of the environment) is stored. in normal operation the capacitance is periodically measured and compared to the stored reference value, if the measured capacitance differs from the stored reference value by more than a register defined threshold, then an interrupt is sent to the external controller. functional overview ST25R3911B 12/129 docid029656 rev 2 1.1.6 external field detector the external field detector is a low power blo ck used in nfc mode to detect the presence of an external rf field. it supports two differen t detection thresholds, peer detection threshold and collision avoidance threshold. the peer de tection threshold is used in the nfcip-1 target mode to detect the presence of an in itiator field, and is also used in active communication initiator mode to detect the activation of the target field. the collision avoidance threshold is used to detect the presence of an rf field during the nfcip-1 rf collision avoidance procedure. 1.1.7 quartz crystal oscillator the quartz crystal oscillator can operate with 13.56 mh z and 27.12 mhz crystals. at start-up the transconductance of the oscillator is increa sed to achieve a fast start-up. the start-up time varies with crystal type, temperatur e and other para meters, hence the oscillator amplitude is observed and an inte rrupt is sent when stable o scillator operation is reached. the use of a 27.12 mhz crystal is mandatory for vhbr operation. the oscillator block also provides a clock signal to the external microcontroller (mcu_clk), according to the settings in the io configuration register 1 . 1.1.8 power supply regulators integrated power supply regulators ensure a high power supply rejection ratio for the complete reader system. if the reader s ystem psrr has to be improved, the command adjust regulators is sent. as a result of this command, the power supply level of v dd is measured in maximum load conditions and the regulated voltage reference is set 250 mv below this measured level to assure a stable regulated supply. the resulting regulated voltage is stored in the regulator and timer display register . it is also possible to define regulated voltage by writing to the regulator voltage control register . to decouple any noise sources from different parts of the ic there are three regulators integrated with separated external blocking capa citors (the regulated voltage of all of them is the same in 3.3 v supply mode). one regula tor is for the analog blocks, one for the digital blocks, and one for the antenna drivers. this block additionally generates a refe rence voltage for the analog processing (agd - analog ground). this voltage also ha s an associated external buffer capacitor. 1.1.9 por and bias this block provides the bias current and the re ference voltages to all other blocks. it also incorporates a power on reset (por) circuit th at provides a reset at power-up and at low supply voltage levels. 1.1.10 rc oscillator and wake-up timer the ST25R3911B in cludes several possibilities of low power detection of card presence (capacitive sensor, phase measurement, amp litude measurem ent). the rc oscillator and the register configurable wake-up timer are used to schedule the periodic card presence detection. docid029656 rev 2 13/129 ST25R3911B functional overview 71 1.1.11 iso-14443 and nfcip-1 framing this block performs framing for receive and transmit according to the selected iso mode and bit rate settings. in reception it takes the demodulated sub-carrier signal from the receiver. it recognizes the sof, eof and data bits, performs parity and crc check, organizes the received data in bytes and places them in the fifo. during transmit, it operates inversely, it ta kes bytes from the fifo, generates parity and crc bits, adds sof and eof and performs final encoding before passing the modulation signal to the transmitter. in transparent mode, the framing and fifo ar e bypassed, the digitized sub-carrier signal (the receiver output), is directly sent to the miso pin, and th e signal applied to the mosi pin is directly used to modulate the transmitter. 1.1.12 fifo the ST25R3911B contains a 96-byte fifo. depending on the mode, it contains either data that has been received or data to be transmitted. 1.1.13 control logic the control logic contains i/o registers that defi ne operation of device. 1.1.14 spi a 4-wire serial peripheral interface (spi) is used for communication between the external microcontroller and the ST25R3911B. 1.2 application information the minimum configurations required to operate the ST25R3911B are shown in figure 2 and figure 3 . functional overview ST25R3911B 14/129 docid029656 rev 2 figure 2. minimum configuratio n with single sided antenna dr iving (including emc filter) figure 3. minimum configurati on with differential antenna driving (including emc filter) 0 6 9 6 7 5 % 9 ' ' 6 6 0 , 6 2 0 2 6 , 6 & / . , 5 4 0 & 8 b & / . 5 ) 5 ) 5 ) , 5 ) , 0 & 8 w r 9 7 5 , 0 b [ 7 5 , 0 b [ $ * ' 9 6 6 9 6 3 b $ 9 6 3 b 5 ) 9 6 1 b 5 ) 9 6 1 b $ 9 ' ' b , 2 ; 7 , ; 7 2 w r 9 9 6 3 b ' 9 6 1 b ' $ q w h q q d f r l o & 6 2 & 6 , 0 6 9 6 7 5 % 9 ' ' 6 6 0 , 6 2 0 2 6 , 6 & / . , 5 4 0 & 8 b & / . 5 ) 5 ) 5 ) , 5 ) , 0 & 8 w r 9 7 5 , 0 b [ 7 5 , 0 b [ $ * ' 9 6 6 9 6 3 b $ 9 6 3 b 5 ) 9 6 1 b 5 ) 9 6 1 b $ 9 ' ' b , 2 ; 7 , ; 7 2 w r 9 9 6 3 b ' 9 6 1 b ' $ q w h q q d f r l o & 6 2 & 6 , docid029656 rev 2 15/129 ST25R3911B functional overview 71 1.2.1 operating modes the ST25R3911B operating mode is defined by the contents of the operation control register . at power-up all bits of the operation control register are set to 0, the ST25R3911B is in power-down mode. in this mode afe static po wer consumption is minimized, only the por and part of the bias are active, while the regulators are transparent and are not operating. the spi is still functional in this mode so all settings of iso mode definition and configuration registers can be done. control bit en (bit 7 of the operation control register ) is controlling the quartz crystal oscillator and regulators. when this bit is set, the device enters in ready mode. in this mode the quartz crystal oscilla tor and regulators are enabled. an interrupt is sent to inform the microcontroller when the oscillator frequency is stable. enable of receiver and transmitter are separated so it is possible to operate one without switching on the other (control bits rx_en and tx_en). in some cases this may be useful, if the reader field has to be maintained and th ere is no transponder response expected, the receiver can be switched-off to save curren t. another example is the nfcip-1 active communication receive mode in which the rf fiel d is generated by the initiator and only the receiver operates. asserting the operation control register bit wu while the other bits are set to 0 puts the ST25R3911B into the wake-up mode that is used to perform low power detection of card presence. in this mode the low power rc osc illator and register conf igurable wake-up timer are used to schedule periodic measurement(s). when a difference of the measured value vs. the predefined reference is detected an interrupt is sent to wake-up the microcontroller. 1.2.2 transmitter the transmitter contains two identical push-pull driver blocks connected to the pins rfo1 and rfo2. these drivers are differentially drivin g the external antenna lc tank. it is also possible to operate only one of the two drivers by setting the io configuration register 1 bit single to 1. each driver is composed of eight segments having binary weighted output resistance. the msb segment ty pical on resistance is 2 ? , when all segments are turned on; the output resistance is typically 1 ? . all segments are turned on to define the normal transmission (non-modulated) level. it is also possible to switch off certain segments when driving the non-modulated level to reduce the am plitude of the signal on the antenna and/or to reduce the antenna q factor without making any hardware changes. the rfo normal level definition register defines which segments are turned on to define the normal transmission (non-modulated) level. default setting is that all segments are turned on. using the single driver mode the number of th e antenna lc tank components (and therefore the cost) is halved, but also the output power is reduced. in single mode it is possible to connect two antenna lc tanks to the two rfo outputs and multiplex between them by controlling the io configuration register 1 bit rfo2. in order to transmit the data the transmitter output level needs to be modulated. both am and ook modulation are supported. the type of modulation is defined by setting the bit tr_am in the auxiliary definition register . during the ook modulation (for example iso1 4443a) the transmitter drivers stop driving the carrier frequency. as consequence the am plitude of the antenna lc tank oscillation decays, the time constant of the decay is defin ed with the lc tank q factor. the decay time in case of ook modulation can be shortened by asserting the auxiliary definition register functional overview ST25R3911B 16/129 docid029656 rev 2 bit ook_hr. when this bit is set to logic one the drivers are put in tristate during the ook modulation. am modulation (for example iso14443b) is done by increasing the output driver impedance during the modulation time. this is done by reducing the number of driver segments that are turned on. the am modulated level can be automatically adjusted to the target modulation depth by defining the target modulation depth in the am modulation depth control register and sending the calibrate modulation depth direct command. refer to section 1.2.20: am modulation depth: definition and calibration for further details. slow transmitter ramping when the transmitter is enabled it starts to drive the antenna lc tank with full power, the ramping of the field emitted by antenna is defined by antenna lc tank q factor. however there are some reader systems where the reader field has to ramp up with a longer transition time when it is enabled. the stif (syndicat des transports d'ile de france) specification requires a transition time from 10% to 90% of field longer than or equal to 10 s.the ST25R3911B supports that feature. it is realized by collapsing vsp_rf regulated voltage when transmitter is disabled and ramping it when transmitter is enabled. typical transition time is 15 s at 3 v supply and 20 s at 5 v supply. procedure to implement the slow transition: 1. when transmitter is disabled set io configuration register 2 bit slow_up to 1. keep this state for at least 2 ms to allow discharge of vsp_rf. 2. enable transm itter, its output will ramp slowly. 3. before sending any command set the bit slow_up back to 0. 1.2.3 receiver the receiver performs demodulation of the transponder sub-carrier modulation that is superimposed on the 13.56 mhz carrier frequency. it performs am and/or pm demodulation, amplification, band-pass filtering and digitaliz ation of sub-carrier si gnals. additionally it performs rssi measurement, automatic gain control (agc) and squelch. in typical applications the receiver inputs rfi1 and rfi2 are outputs of capacitor dividers connected directly to the terminals of the an tenna coil. this concept ensures that the two input signals are in phase with the voltage on the antenna coil. the design of the capacitive divider must ensure that the rfi1 and rfi2 input signal peak values do not exceed the v sp_a supply voltage level. the receiver comprises two complete receive channels, one for the am demodulation and another one for the pm demodulation. in case both channels are active the selection of the channel used for reception framing is done auto matically by the receive framing logic. the receiver is switched on when operation control register bit rx_en is set to one. additionally the operation control register contains bits rx_chn and rx_man; rx_chn defines whether both, am and pm, demodulation channels will be active or only one of them, while bit rx_man defines the channel selection mode in ca se both channels are active (automatic or manual). operation of the rece iver is controlled by four re ceiver configuration registers. the operation of the receiver is additionally controlled by the signal rx_on that is set high when a modulated signal is expected on the rece iver input. this signal is used to control rssi and agc and also enables processing of the receiver output by the framing logic. signal rx_on is automatically set to high afte r the mask receive timer expires. signal rx_on docid029656 rev 2 17/129 ST25R3911B functional overview 71 can also be directly controlled by the contro ller by sending direct commands mask receive data and unmask receive data. figure 4 details the receiver block diagram. figure 4. receiver block diagram demodulation stage the first stage performs demodulation of the transponder sub-carrier signal, superimposed on the hf field carrier. two different blocks are implemented for am demodulation: ? peak detector ? am demodulator mixer. the choice of the used demodulator is made by the receiver configuration register 1 bit amd_sel. the peak detector performs am demodulation using a peak follower. both the positive and negative peaks are tracked to suppress any common mode signal. the peak detector is limited in speed; it can operate for sub-carrier frequencies up to fc/8 (1700 khz). its demodulation gain is g = 0.7. its input is ta ken from one demodulator input only (usually rfi1). the am demodulator mixer uses synchronous rectification of both receiver inputs (rfi1 and rfi2). its gain is g = 0.55. the mixer demo dulator is optimized for vhbr sub-carrier frequencies (fc/8 and higher). for sub-carrier frequency fc/8 (1700 khz) both peak follower and mixer demodulator can be used, while for fc/4 and fc/2 only the mixer demodulator can be used. pm demodulation is also done by a mixer. the pm demodulator mixer has differential outputs with 60 mv differential signal for 1% phase change (16.67 mv / ). its operation is optimized for sub-carrier frequ encies up to fc/8 (1700 khz). 0 6 9 3 h d n g h w h f w r u $ * & 6 t x h o f k 5 6 6 , u h f ! $ * & 6 t x h o f k 5 6 6 , u h f ! u h f ! u h f ! u h f ! u h f ! ' l j l w d o v x e f d u u l h u $ & f r x s o l q j v w j d l q v w d j h / r z s d v v q g j d l q v w d j h + l j k s d v v u g j d l q v w d j h ' l j l w l ] l q j v w d j h ' h p r g x o d w l r q v w d j h 0 8 ; 3 0 ' h p r g x o d w r u 0 l [ h u u h f ! u h f ! 5 ) b , 1 5 ) b , 1 5 6 6 , b $ 0 ! 5 6 6 , b 3 0 ! 5 ; b r q v j b r q $ 0 ' h p r g x o d w r u 0 l [ h u ' l j l w d o v x e f d u u l h u functional overview ST25R3911B 18/129 docid029656 rev 2 in case the demodulation is done externally, it is possible to multiple x the lf signals applied to pins rfi1 and rfi2 directly to the gain and filtering stage by selecting the receiver configuration register 2 bit lf_en. filtering and gain stages the receiver chain has band pass filtering charac teristics. filtering is optimized to pass sub-carrier frequencies while rejecting carrier frequency and low frequency noise and dc component. filtering and gain is implemented in three stages, where th e first and the last stage have first order high pass characteristics, and the second stage has second order low pass characteristic. gain and filtering characteristics can be optimized by writing the receiver configuration register 1 (filtering), the receiver configuration register 3 (gain in first stage) and the receiver configuration register 4 (gain in second and third stage). the gain of the first stage is about 20 db and can be reduced in six 2.5 db steps. there is also a special boost mode available, which boos ts the maximum gain by additional 5.5 db. in case of vhbr (fc/8 and fc/4) the gain is lower. the first stage gain can only be modified by writing receiver configuration register 3 . the default setting of this register is the minimum gain. the default first stage zero is set at 60 khz, it can also be lowered to 40 khz or to 12 khz by writing option bits in the receiver configuration register 1 . the control of the first and third stage zeros is done with common control bits (see table 1 ). the gain in the second and third stage is 23 db and can be reduced in six 3 db steps. the gain of these two stages is included in the ag c and squelch loops. it can also be manually set in receiver configur ation register 4 . sending of direct command reset rx gain is necessary to reset the agc, squelch and r ssi block. sending this command clears the current squelch setting and loads the gain reduction configuration from receiver configuration register 4 into the internal shadow registers of the agc and squelch block. the second stage has a second order low pass filtering characteristic, the pass band is adjusted according to the sub-carrier frequency using the bits lp2 to lp0 of the receiver configuration register 1 . see table 2 for -1 db cut-off frequency for different settings. table 1. first and third stage zero setting rec1<2> h200 rec1<1> h80 rec1<0> z12k first stage zero third stage zero 0 0 0 60 khz 400 khz 1 0 0 60 khz 200 khz 0 1 0 40 khz 80 khz 0 0 1 12 khz 200 khz 0 1 1 12 khz 80 khz 1 0 1 12 khz 200 khz others not used docid029656 rev 2 19/129 ST25R3911B functional overview 71 table 3 provides information on the recommended filter settings. for all supported operation modes and receive bit rates there is an aut omatic preset defined, additionally some alternatives are listed. automatic preset is do ne by sending direct command analog preset. there is no automatic preset for stream and transparent modes. since the selection of the filter characteristics also modifies gain, the ga in range for different filter settings is also listed. digitizing stage the digitizing stage produces a digital represent ation of the sub-carrier signal coming from the receiver. this digital signal is then processe d by the receiver framing logic. the digitizing stage consists of a window comparator with ad justable digitizing window (five possible table 2. low pass control rec1<5> lp2 rec1<4> lp1 rec1<3> lp0 -1 db point 0 0 0 1200 khz 001600 khz 011300 khz 1002 mhz 1017 mhz others not used table 3. receiver filter selection and gain range rec1<5:3>lp<2:0> rec1<2>h200 rec1<1>h80 rec1<0>z12k gain (db) comments max all min1 max23 max1 min23 min all with boost 000 0 0 0 43.4 28.0 26.4 11.0 49.8 automatic preset for iso14443a fc/128 and nfc forum type 1 tag 000 1 0 0 44.0 29.0 27.5 12.0 49.7 automatic preset for iso14443b fc/128 iso14443 fc/64 001 1 0 0 44.3 29 27.0 11.7 49.8 recommended for 424/484 khz sub-carrier 000 0 1 0 41.1 25.8 23.6 8.3 46.8 alternative choice for iso14443 fc/32 and fc/16 100 0 1 0 32.0 17.0 17.2 2.0 37.6 automatic preset for iso14443 fc/32 and fc/16 alternative choice fo r fc/8 (1.7 kb/s) 100 0 0 0 32.0 17.0 17.2 2.0 37.6 alternativ e choice for fc/8 (1.7 kb/s) 000 0 1 1 41.1 25.8 23.6 8.3 46.8 automatic preset felica ? (fc/64, fc/32) alternative choice for iso14443 fc/32 and fc/16 101 0 1 0 30.0 20.0 12.0 2.0 34.0 alternat ive choice for fc/8 and fc/4 101 1 0 0 30.0 20.0 12.0 2.0 34.0 automatic preset for fc/8 and fc/4 000 1 0 1 36.5 21.5 24.9 9.9 41.5 automatic pr eset for nfcip-1 (i nitiator and target) functional overview ST25R3911B 20/129 docid029656 rev 2 settings, 3 db steps, adjustment range from 33 mv to 120 mv). adjustment of the digitizing window is included in the agc and squelch loops. in addi tion, the digitizing window can also be set manually in the receiver configuration register 4 . agc, squelch and rssi as mentioned above, the second and third gain stage gain and the digitizing stage window are included in the agc and squelch loops. elev en settings are available. the default state features minimum digitizer window and maximum gain. the first four steps increase the digitizer window in 3 db steps, the next six step s additionally reduce the gain in the second and third gain stage, again in 3 db steps. the initial setting with whom squelch and agc start is defined in receiver configuration register 4 . the gain reduction state register displays the actual state of gain that results from squelch, agc and initial settings in receiver configuration register 4 . during bit anticollision like type a, the agc should be disabled. squelch this feature is designed for operation of th e receiver in noisy conditions. the noise can come from tags (caused by the processing of reader commands), or it can come from a noisy environment. this noise may be misinter preted as start of transponder response, resulting in dec oding errors. during execution of the squelch procedure th e output of the digitizing comparator is observed. in case there are more than two transitions on this output in a 50 s time period, the receiver gain is reduced by 3 db, and t he output is observed during the next 50 s. this procedure is repeated until the number of transitions in 50 s is lower or equal to two, or until the maximum gain reduction is reached. this gain reduction can be cleared sending the direct command reset rx gain. there are two possibilities of performing squelch: automati c mode and using the direct command squelch. 1. automatic mode is enabled in case bit sqm_dyn in the receiver configuration register 2 is set. it is activated automatically 18.88 s after end of tx and is terminated when the mask receive timer expires. this mode is primarily intended to suppress noise generated by tag processing during the time when a tag response is not expected (covered by mask receive timer). 2. command squelch is accepted in case it is sent when signal rx_on is low. it can be used when the time window in which noise is present is known by the controller. agc agc (automatic gain control) is used to re duce gain to keep the receiver chain out of saturation. with gain properly adjusted the demodu lation process is also less influenced by system noise. agc action starts when signal rx_on is asserted high and is reset when it is reset to low. at the high to low transitions of the rx_on signal t he state of the receiver gain is stored in the gain reduction state register . reading this register at a later stage gives information on the gain setting used during last reception. when agc is switched on the receiver gain is re duced so that the input to the digitizer stage is not saturated. the agc system comprises a comparator with a window 3.5 times larger than that of the digitizing window comparator. w hen the agc function is enabled the gain is reduced until there are no transitions on the output of its window comparator. this docid029656 rev 2 21/129 ST25R3911B functional overview 71 procedure ensures that the input to the digitizi ng window comparator is less than 3.5 times larger than its threshold. agc operation is controlled by the control bits agc_en, agc_m and agc_fast in the receiver configuration register 2 . bit agc_en enables the agc operation, bit agc_m defines the agc mode, and bit agc_alg defines the agc algorithm. two agc modes are available. the agc can operate during the complete rx process (as long as signal rx_on is high), or it can be enabled only during the first eight sub-carrier pulses. two agc algorithms are available. the agc can either start by presetting code 4h (max digitizer window, max gain) or by resetting the code to 0h (min digitizer window, max gain). the algorithm with preset code is faster, theref ore it is recommended for protocols with short sof (like iso14443a fc/128). default agc settings are: ? agc is enabled ? agc operates during complete rx process ? algorithm with preset is used. rssi the receiver also performs the rssi (receive d signal strength indicator) measurement for both channels. the rssi measurement is started after the rising edge of rx_on. it stays active as long as signal rx_on is high, it is frozen while rx_on is low. the rssi is a peak hold system, and the value can only increase from the initial zero value. every time the agc reduces the gain the rssi measurement is rese t and starts from zero. result of rssi measurements is a 4-bit value that can be observed by reading the rssi display register . the lsb step is 2.8 db, and the maximum code is dh (13d). since the rssi measurement is of peak hold type the rssi measurement result does not follow any variations in the sign al strength (the highest value will be kept). in order to follow rssi variations it is possible to reset the rssi bits and restart the measurement by sending the direct command clear rssi. receiver in nfcip-1 active communication mode there are several features built into the rece iver to enable reliable reception of active nfcip-1 communication. all these settings are au tomatically preset by sending the direct command analog preset after the nfcip-1 mode has been configured. in addition to the filtering options, there are two nfcip-1 active communication mode specific configuration bits stored in the receiver configuration register 3 . bit lim enables clipping circuits that are posi tioned after the first and second gain stages. the function of the clipping circuits is to limit the signal level for the following filtering stage (when the nfcip-1 peer is close the input signal level can be quite high). bit rg_nfc forces gain reduction of second and th ird filtering stage to -6 db while keeping the digitizer comparator window at maximum level. 1.2.4 capacitive sensor the capacitive sensor block ( figure 5 ) gives the possibility of lo w power detection of tag presence. functional overview ST25R3911B 22/129 docid029656 rev 2 the capacitive measurement system comprise s two electrodes. one is the excitation electrode emitting an electrical field of a fi xed frequency in the range of a few hundred khz (cso) and the second one is the sensing elec trode (csi). the amount of charge generated in the sensing electrode represents the capacitance between the two electrodes. the capacitive sensor electrodes are tolerant to parasitic capacitance to ground (up to 25 pf) and to input leakage (up to 1 m ? ). since the charge on the sensing electrode is generated with the frequency of the excitation electrode, a synchronous rectif ier is used to detect it. th is ensures good rejection of interference and high tolerance to parasitic ca pacitances (to all nodes except the excitation electrode). the synchronous rectifier output is a dc voltage linearly proportional to the capacitance between the excitation and sensing electrode. the output dc voltage is converted by the a/d converter in absolute mode. the result is stored in the a/d converter output register (see also section 1.2.8: a/d converter ). figure 5. capacitive sensor block diagram any conductive object (human hand or ta g antenna windings) approaching the two electrodes changes the capacitance between th e excitation and sensing electrode as it 'shortens' the distance between the two by pr oviding conductance on the part of the path between the two electrodes. the capacitance measurement is started by sending the direct command measure capacitance. the ST25R3911B can also be configured to automatically wake-up and perform periodic capacitance measurements. the result is compared to a stored reference or to an average of previous measurements a nd in case the difference is greater than a predefined value an irq is triggered to wake-up the controller (see also section 1.2.5: wake-up mode ). the capacitive sensor gain can be adjusted in capacitive sensor control register . the default gain is 2.8 v/pf (typical value), the ma ximum gain is 6.5 v/pf (typical value). since the lsb of the a/d converter corresponds to approximately 7.8 mv, the default gain results in a sensitivity of 2.8 ff/lsb (1.2 ff/lsb in ca se of maximum gain). the duration of the capacitance measurement is 200 s, and the current consumption during the measurement is 1.1 ma (typical va lue). as an example, if the capacitive measurement is performed every 100 ms in wake-up mode, then the resulting average current consumption is 5.8 a (3.6 a is the standby consumption in wake-up mode). 0 6 9 2 v f l o o d w r u $ ' f r q y h u w h u 6 \ q f k u r q r x v u h f w l i l h u & 6 2 & 6 , docid029656 rev 2 23/129 ST25R3911B functional overview 71 capacitor sensor calibration the capacitive sensor comprises a calibration unit that intern ally compensates the parasitic capacitances between csi and cso, thus l eaving full measurement range for information about capacitance variation. five bits are used to control the calibration. the minimum calibration step and the available calib ration range are, respectively, 0.1 pf and 3.1 pf. the calibration can be done manually by writing to the capacitive sensor control register or automatically by sending the direct command ca librate capacitive sensor. the status of the calibrate capacitive sensor command and the re sulting calibration value are stored in the capacitive sensor display register . in order to avoid interf erence of the capacitive sensor with the xtal oscillato r and the reader magnetic field and to assure repetitive resu lts it is strongly recommended to perform capacitance measurement and calibration in power-down mode only. 1.2.5 wake-up mode asserting the operation control register bit wu while the other bits are set to 0 puts the ST25R3911B in wake-up mode, used to perf orm low power detection of card presence. the ST25R3911B incl udes several possibilities of low po wer detection of a card presence (capacitive sensor, phase measurement, amplit ude measurement). an integrated low power 32 khz rc oscillator and a regi ster configurable wake-up timer are used to schedule periodic detection. usually the presence of a card is detected by a so-called polling loop. in this process the reader field is periodically turned on and th e controller checks whether a card is present using rf commands. this procedure consumes a lot of energy since the reader field has to be turned on for 5 ms before a command can be issued. low power detection of card presence is performed by detecting a change in the reader environment, produced by a card. when a change is detected, an interrupt is sent to the controller. as a result, the controller ca n perform a regular polling loop. in the wake-up mode the ST25R3911B periodically performs the configured reader environment measurements and sends an irq to the controller when a difference to the configured reference value is detected. detection of card presence can be done by performing phase,amplitude and capacitive sensor measurements. presence of a card close to the reader antenna coil produces a change of the antenna lc tank signal phase and amplitude. the reader field activation time needed to perform the phase or the amplitude measurement is extremely short (~20 s) compared to the activation time needed to send a pr otocol activation command. additionally the power level during the measurement can be lower than the power level during normal operation since the card does not have to be powered to produce a coupling effect. the emitted power can be reduced by changing the rfo normal level definition register . the capacitive sensor detects a change of the parasitic capacitance between the two excitation electrodes. this change in capaci tance can be caused by a card antenna or a hand holding the card. see section 1.1.5: capacitive sensor for a detailed information on the capacitive sensor. the registers on locations from 31h to 3dh are dedicated to wake-up timer configuration and display. the wake-up timer control register is the main wake-up mode configuration functional overview ST25R3911B 24/129 docid029656 rev 2 register. the timeout period between the succ essive detections and the measurements are selected in this register. timeouts in the range from 10 to 800 ms are available, 100 ms is the default value. any combination of availa ble measurements can be selected (one, two or all of them). the next twelve registers (32h to 3dh) are configuring the three possible detection measurements and storing the results, four registers are used for each measurement. an irq is sent when the difference between a measured value and the reference value is larger than the configured threshold value. there are two possible definitions for the reference value: 1. the ST25R3911B can calculate the reference based on previous measurements (auto-averaging) 2. the controller determines the reference and stores it in a register the first register in the series of four is the amplitude measurement configuration register . the difference to the reference value that tri ggers the irq, the method of reference value definition and the weight of the last measurement result in case of auto-averaging are defined in this register. the next register is storing the reference value in case the reference is defined by the controller. the following two registers are display registers. the first one stores the auto-averaging reference, and the second one stores the result of the last measurement. the wake-up mode configuration registers have to be configured before the wake-up mode is entered. any modification of the wake -up mode configuration while it is active may result in unpredictable behavior. auto-averaging in case of auto-averaging the reference val ue is recalculated after every measurement as newaverage = oldaverage + (measuredvalue - oldaverage) / weight the calculation is done on 13 bits to have suff icient precision.the auto-averaging process is initialized when the wake-up mode is entered for the first time after initialization (at power- up or after set default command). the initial value is taken from the measurement display registers (for example amplitude measurement display register ) until the content of this register is not zero. every measurement configuration register contains a bit that defines whether the measurement that causes an interrupt is take n in account for the average value calculation (for example bit am_aam of the amplitude measurement configuration register ). 1.2.6 quartz crystal oscillator the quartz crystal oscillato r can operate with 13.56 mhz and 27.12 mhz crystals. the operation of quartz crystal os cillator is enabled when the operation control register bit en is set to one. an inte rrupt is sent to inform the microcon troller when the osc illator frequency is stable (see section 1.3.24: main interrupt register ). the status of oscillator can be observed by observing the auxiliary display register bit osc_ok. this bit is set to ?1? wh en oscillator frequency is stable. the oscillator is based on an inverter stage supplied by a controlled current source. a feedback loop is controlling th e bias current in or der to regulate amplitude on xti pin to 1 v pp . docid029656 rev 2 25/129 ST25R3911B functional overview 71 to enable a fast reader start-up an interrupt is sent w hen the oscillator amplitude exceeds 750 mv pp . division by two ensures that 13.56 mhz signal has a duty cycle of 50%, which is better for the transmitter performance (no pw distortion) . use of 27.12 mhz crystal is therefore recommended for better performance. in case of 13.56 mhz crystal, the bias current of stage that is digitizing oscillator signal is increased to assure as low pw distortion as possible. note: in case of vhbr reception (b it rates fc/8 and above) it is mandatory to use the 27.12 mhz crystal since high frequency cloc k is needed for receive framing. the oscillator output is also used to drive a clock signal output pin mcu_clk) that can be used by the external microcontroller. the mcu_clk pin is configured in the io configuration register 2 . 1.2.7 timers the ST25R3911B contains several timers that eliminate the need to run counters in the controller, thus reducing the effort of the controller code implementation and improve portability of code to different controllers. every timer has one or more associated c onfiguration registers in which the timeout duration and different operating modes are defin ed. these configuration registers have to be set while the corresponding timer is not runn ing. any modification of timer configuration while the timer is active may result in unpredictable behavior. all timers except the wake-up timer are stopped by direct command clear. note: in case bit nrt_emv in the general purpose and no-response timer control register is set to one, the no-response timer is not stopped mask receive timer and no-response timer mask receive timer and no-response timer are both automatically started at the end of transmission (at the end of eof). mask receive timer the mask receive timer is blocking the receiv er and reception process in framing logic by keeping the rx_on signal low after the end of tx during the time the tag reply is not expected. while the mask receive timer is running, the squelch is automatically turned on (if enabled). mask receive timer does not produce an irq. the mask receive timer timeout is configured in the mask receive timer register . in the nfcip-1 active communication mode th e mask receive timer is started when the peer nfc device (a device with whom communication is going on) switches on its field. the mask receive timer has a special use in the low power initial nfc target mode. after the initiator field has been detected the cont roller turns on the osc illator, regulator and receiver. mask receive timer is started by sending direct command start mask receive timer. after the mask receive timer expires the receiver output starts to be observed to detect start of the initiator message. in th is mode the mask receive timer clock is additionally divided by eight it (one count is 512/fc) to cover range up to about 9.6 ms. functional overview ST25R3911B 26/129 docid029656 rev 2 no-response timer as its name indicates, this ti mer is intended to observe whether a tag response is detected in a configured time started by end of transmission. the i_nre flag in the timer and nfc interrupt register is signaling interrupt events resulting from this timer timeout. the no-response timer is configured by writing the two registers no-response timer register 1 and no-response timer register 2 . operation options of the no-response timer are defined by setting bits nrt_emv and nrt_step in the general purpose and no-response timer control register . bit nrt_step configures the time step of th e no-response timer. two steps are available, 64/fc (4.72 s) to cover range up to 309 ms, and 4096/fc, covering the range up to 19.8 s. bit nrt_emv controls the timer operation mode: ? when this bit is set to 0 (d efault mode) the irq is produced in case the no-response timer expires before a start of a tag reply is detected and rx_on is forced to low to stop receiver process. in the opposite case, when start of a tag reply is detected before timeout, the timer is stopped, and no irq is produced. ? when this bit is set to 1 the timer unconditiona lly produces an irq when it expires, it is also not stopped by direct command clear. this means that irq is independent of the fact whether or not a tag reply was detected. in case at the moment of timeout a tag reply is being processed no other action is taken, in the opposite case, when no tag response is being processed additionally the signal rx_on is forced to low to stop receive process. the no-response timer can also be started using direct command start no-response timer. the intention of this command is to extend the no-response timer timeout beyond the range defined in the no-response timer cont rol registers. in case this command is sent while the timer is running, it is reset and restarted. in nfcip-1 active communication mode the no-response timer cannot be started using the direct command. in case this timer expires before the peer nf c device (a device with whom communication is going on) switches on its field an interrupt is sent. in all modes, where timer is set to nonzero valu e, it is a must that m_txe is not set and interrupt i_txe is read via spi for synchronization between transmitter and timer. general purpose timer the triggering of the general purpose timer is configured by setting the general purpose and no-response timer control register . it can be used to su rvey the duration of the reception process (triggering by start of reception, after sof) or to time out the pcd to picc response time (triggered by end of re ception, after eof). in the nfcip-1 active communication mode it is used to timeout the field switching off. in all cases an irq is sent when it expires. the general purpose timer can also be started by sending the direct command start general purpose timer. in case this command is sent while the timer is running, it is reset and restarted. wake-up timer wake timer is primarily used in the wake-up mode (see section 1.2.5: wake-up mode ). additionally it can be used by sending a direct command start wake-up timer. this command is accepted in any operation mode except wake-up mode. when this command is sent the rc oscillator used as clock sour ce for wake-up timer is started, timeout is docid029656 rev 2 27/129 ST25R3911B functional overview 71 defined by setting in the wake-up timer control register . when the timer expires, an irq with the i_wt flag in the error and wake-up interrupt register is sent. wake-up timer is useful in the low power operation mode, in which other timers cannot be used (in the low power operatio n mode the crystal oscillator, which is clock source for the other timers, is not running). note: the tolerance of wake-up timer timeout is defined by tolerance of the rc oscillator. 1.2.8 a/d converter the ST25R3911B contains an 8-bit successive approximation a/d converter. inputs to the a/d converter can be multiplexed from differ ent sources to be used in several direct commands and adjustment procedures. the result of the last a/d conversion is stored in the a/d converter output register . the a/d converter has two operati ng modes, absolute and relative. ? in absolute mode the low reference is 0 v and the high reference is 2 v. this means that a/d converter input range is from 0 to 2 v, 00h code means input is 0 v or lower, ffh means that input is 2 v - 1 lsb or higher (lsb is 7.8125 mv). ? in relative mode low reference is 1/6 of v sp_a and high reference is 5/6 of v sp_a , so the input range is from 1/6 to 5/6 v sp_a . relative mode is only used in phase measurem ent (phase detector output is proportional to power supply). in all other cases absolute mode is used. 1.2.9 phase and am plitude detector this block is used to provide input to a/d co nverter to perform measurements of amplitude and phase, expected by dire ct commands measure amplitude and measure phase. several phase and amplitude measurements are also performed by direct commands calibrate modulation depth and calibrate antenna. phase detector the phase detector is observing phase differ ence between the transmitter output signals (rfo1 and rfo2) and the receiver input signals rfi1 and rfi2, which are proportional to the signal on the antenna lc tank. these signals are first elaborated by digitizing comparators, then digitized signals are proc essed by a phase detector with a strong low pass filter to get average phase difference. the phase detector output is inversely proporti onal to the phase difference between the two inputs. the 90 phase shift results in v sp_a /2 output voltage, in case both inputs are in phase output voltage is v sp_a , in case they are in opposite phase output voltage is 0 v. during execution of direct command measure phase this output is multiplexed to a/d converter input (a/d converter is in relati ve mode during execution of command measure phase). since the a/d converter range is from 1/6 to 5/6 v sp_a the actual phase detector range is from 30o to 150o. figure 6 and figure 7 show the two inputs and the output of phase detector, respectively, in case of 90o and 135o shifts. functional overview ST25R3911B 28/129 docid029656 rev 2 figure 6. phase detector inputs and output in case of 90o phase shift figure 7. phase detector inputs and output in case of 135o phase shift amplitude detector signals from pins rfi1 and rfi2 are used as in puts to the self-mixing stage. the output of this stage is a dc voltage proportional to amplitude of signal on pins rfi1 and rfi2. during execution of direct command measure amplitude this output is multiplexed to a/d converter input. 1.2.10 external field detector the external field detector is used to detect the presence of an external device generating an rf field. it is automatically switched on in nfcip-1 active communication modes; it can also be used in other modes. the external field detector supports two different detection thresholds, peer detection threshold a nd collision avoidance threshold. the two thresholds can be independently set by writing the external field detector threshold register . the actual state of the external field detector output can be checked by reading the auxiliary display register . input to this block is the signal from the rfi1 pin. 0 6 9 9 6 3 b $ 9 6 3 b $ 9 6 3 b $ 9 6 3 b $ , q s x w , q s x w 2 x w s x w 0 6 9 9 6 3 b $ 9 6 3 b $ 9 6 3 b $ 9 6 3 b $ , q s x w , q s x w 2 x w s x w docid029656 rev 2 29/129 ST25R3911B functional overview 71 peer detection threshold this threshold is used to detect the field emitted by peer nfc device with whom nfc communication is going on (initiator field in case the ST25R3911B is a target and the opposite, target field in case the ST25R3911B isan initiator). it can be selected in the range from 75 to 800 mv pp . when this threshold is enabled the external field detector is in low power mode. an interrupt is generated when an ex ternal field is detected and also when it is switched off. with such implementation it ca n also be used to detect the moment when the external field disappears. this is useful to detect the moment when the peer nfc device (it can be either an initiator or a target) has stopped emitting an rf field. the external field detector is automatically enabled in the low power peer detection mode when nfcip-1 mode (initiator or target) is selected in the bit rate definition register . additionally it can be enabled by setting bit en_fd in the auxiliary definition register . collision avoidance threshold this threshold is used during the rf collis ion avoidance sequence that is executed by sending nfc field on commands (see nfc field on commands ). it can be selected in the range from 25 to 800 mv pp . 1.2.11 power supply system the ST25R3911B ( figure 8 ) features two positive s upply pins, vdd and vdd_io. vdd is the main power supply pin. it supplies the ST25R3911B blocks through three regulators (vsp_a, vsp_d and vsp_rf). v dd range from 2.4 to 5.5 v is supported. v dd_io is used to define supply level for digital communication pins (/ss, miso, mosi, sclk, irq, mcu_clk). digital communication pins interface with ST25R3911B logic through level shifters, therefore the internal supply voltage can be either higher or lower than v dd_io . v dd_io range from 1.65 to 5.5 v is supported. figure 8. ST25R3911B power supply 0 6 9 3 r z h u g r z q 6 x s s r u w v x s 9 ? 5 9 ! 9 6 3 b 5 ) 5 ( * ( 1 % * 5 $ * & $ 8 7 2 5 ( * 9 6 3 b $ n ? 9 6 3 b ' $ * ' u h j % k u h j $ k 9 6 3 b $ 5 ( * 9 6 3 b ' 5 ( * d g m x v w 9 6 3 b 5 ) 9 ' ' functional overview ST25R3911B 30/129 docid029656 rev 2 figure 8 shows the building blocks of the ST25R3911B power supply system and the signals that control it. the power supply system contains three regulators, a power-down support block, a block generating analog reference voltage (agd) and a block performing automatic power supply adjustment procedure. the three regulators are providing supply to analog blocks (vsp_a), logic (vsp_d) and transmitte r (vsp_rf). the use of vsp _a and vsp_d regulators is mandatory at 5 v power supply to provide regulated voltage to analog and logic blocks that only use 3.3 v devices. the use of vsp_ a and vsp_d regulators at 3 v supply and vsp_rf regulator at any su pply voltage is recommended to impr ove system psrr. regulated voltage can be adjusted automatically to have maximum possible regulated voltage while still having good psrr. all regula tor pins also have co rresponding negative supply pins that are extern ally connected to ground po tential (vss). the reason for separation is in decoupling of noise induced by voltage drops on the internal power supply lines. figure 2 and figure 3 show typical ST25R3911B applicat ion schematics with all regulators used. all regulator pins and agd voltage are buffered with capacitors. recommended blocking capacitor values are detailed in table 4 . regulators have two basic operation modes de pending on supply voltage, 3.3 v supply mode (max 3.6 v) and 5 v supply mode (max 5. 5 v). the supply mode is set by writing bit sup3 v in the io configuration register 2 . default setting is 5 v, hence this bit has to be set to one after power-up in case of 3.3 v supply. in 3.3 v mode all regulators are set to the same regulated voltage in range from 2.4 v to 3.4 v, while in 5 v only the vsp_rf can be set in range from 3.9 v to 5.1 v, while vsp_a and vsp_d are fixed to 3.4 v. the regulators are operating when signal en is high (en is configuration bit in operation control register . when signal en is low the st25r391 1b isare in low power power-down mode. in this mode consumption of the power supply system is also minimized. vsp_rf regulator the intention of this regulator is to improv e psrr of the transmitter (the noise of the transmitter power supply is emitte d and fed back to the receiver). the vsp_rf regulator operation is controlled and observed by wr iting and reading two regulator registers: ? regulator voltage control register controls the regulator mode and regulated voltage. bit reg_s controls regulator mode. in case it is set to 0 (default state) the regulated voltage is set using direct command adjust regulators. when bit reg_s is asserted to 1 regulated voltage is defined by bits rege_3 to rege_1 of the same register. the regulated voltage adjustment range depends on the power supply mode. in case of 5 v supply mode the adjustment range is between 3.9 v and 5.1 v in steps of 120 mv, in table 4. recommended blocking capacitor values pins recommended capacitors agd-vss 1 f, in parallel with 10 nf vsp_a-vsn_a vsp_d-vsn_d 2.2 f, in parallel with 10 nf 2.2 f, in parallel with 10 nf vsp_rf-vsn_rf 2.2 f, in parallel with 10 nf docid029656 rev 2 31/129 ST25R3911B functional overview 71 case of 3.3 v supply mode the adjustment ra nge is from 2.4 v to 3.4 v with steps of 100 mv. default regulated voltage is the maximum one (5.1 v and 3.4 v in case of 5 v and 3.3 v supply mode respectively). ? regulator and timer display register is a read only register that displays actual regulated voltage when regulator is operating. it is especially useful in case of automatic mode, since the actual regulated voltage, which is the result of direct command adjust regulators, can be observed. the vsp_rf regulator also inclu des a current limiter that limit s the regulator typically to current of 200 ma rms in normal operation (500 ma in case of short). in case the transmitter output current higher the 200 ma rms is required, vsp_rf regu lator cannot be used to supply the transmitter, vsp_rf has to be externally conn ected to vdd (c onnection of vsp_rf to supply volt age higher than v dd is not allowed). the voltage drop of the transmitter current is the main source of the ST25R3911B power dissipation. this voltage drop is composed of drop in the transmitter driver and in the drop on vsp_rf regulator. due to this it is re commended to set regulated voltage using direct command adjust regulators. it results in good po wer supply rejection ra tion with relatively low dissipated power due to regulator voltage drop. in power-down mode the vsp_rf regulator is not operating. vsp_rf pin is connecte d to vdd through 1 k ? resistor. connection through resistor s ensures smooth power-up of the system and a smooth transition from power-down mode to other operating modes. vsp_a and vsp_d regulators vsp_a and vsp_d regulators ar e used to supply the st25r 3911b analog and digital blocks respectively. in 3. 3 v mode, vsp_a and vsp_d regula tor are set to the same regulated voltage as the vsp_rf regulator, in 5 v mode vsp_a and vsp_d regulated voltage is fixed to 3.4 v. the use of vsp_a and vsp_d regula tors is obligatory in 5 v mo de since analog and digital blocks supplied with these two pins contain low voltage trans istors that support maximum supply voltage of 3.6 v. in 3.3 v supply mode the use of regulators is strongly recommended in order to improve psrr of analog processing. for low cost applications it is possible to di sable the vsp_d regulator and to supply digital blocks through external shor t between vsp_a and vsp_d (configur ation bit vspd_off in the io configuration register 2 . in case vsp_d regulator is disabled vsp_d can alternatively be supplied from vdd (in 3.3 v mode only) in case vsp_a is not more than 300 mv lower than vdd. power-down support block in the power-down mode the regulators are disabled in order to save current. in this mode a low power power-do wn support block that maintains the vsp_d and vsp_a in below 3.6 v is enabled. typical regulated voltage in this m ode is 3.1 v at 5 v s upply and 2.2 v at 3 v supply. when 3.3 v supply mode is set the power-down support block is disabled, its output is connected to vdd through 1 k ? resistor. typical consumption of power-down support block is 600 na at 5 v supply. functional overview ST25R3911B 32/129 docid029656 rev 2 measurement of supply voltages using direct command measure power supply it is possible to measure vdd and regulated voltages vsp_a, vsp_d, and vsp_rf. 1.2.12 communication with an external microcontroller the ST25R3911B is a slave device and the external microcontroller initiates all communication. communication is performed by a 4-wire serial peripheral interface (spi). the ST25R3911B sends an interrupt request (pin irq) to the microcontroller, which can use clock signal available on pin mcu_ clk when the oscillator is running. serial peripheral interface (spi) while signal /ss is high the spi interface is in reset, while it is low the spi is enabled. it is recommended to keep /ss high whenever the spi is not in use. mosi is sampled at the falling edge of sclk. all communicati on is done in blocks of 8 bits (bytes). first two bits of first byte transmitted after high to low tr ansition of /ss define spi operation mode. msb bit is always transmitted first (valid for address and data). read and write modes support address auto-i ncrementing. this means that if some additional data bytes are sent/read after the address and first data byte, they are written to/read from addresses incremented by ?1?. figure 9 defines possible modes. figure 9. exchange of signals with microcontroller table 5. serial data interface (4-wire interface) signal lines name signal signal level description /ss digital input cmos spi enable (active low) mosi digital input serial data input miso digital output with tristate serial data output sclk digital input clock for serial communication 0 6 9 0 2 6 , 0 , 6 2 , 2 6 7 5 % 0 2 6 , 0 , 6 2 0 , 6 2 0 2 6 , 6 7 5 % 6 h s d u d w h 6 3 , l q s x w d q g r x w s x w v l j q d o v w r 0 & 8 % l g l u h f w l r q d o g d w d , 2 v l j q d o w r 0 & 8 docid029656 rev 2 33/129 ST25R3911B functional overview 71 miso output is usually in tristate, it is only driven when output data is available. due to this the mosi and the miso can be externally shorted to create a bidirectional signal. during the time the miso output is in tris tate, it is possible to switch on a 10 k ? pull down by activating option bits miso_pd1 and miso_pd2 in the io configuration register 2 . table 6 provides information on the spi operation modes. reading and writing of registers is possible in any ST25R3911B operation mode. fifo operations are possible in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. writing data to addressable registers (write mode) figure 10 and figure 11 show cases of writing a single by te and writing mu ltiple bytes with auto-incrementing address. after the spi operatio n mode bits, the address of register to be written is provided. then one or more data bytes are transferred from the spi, always from the msb to the lsb. the data byte is written in register on fa lling edge of its last clock. in case the communication is terminated by putting /ss high before a packet of 8 bits (one byte) is sent, writing of this register is not performed. in case the register on the defined address does not exist or it is a re ad only register no write is performed. table 6. spi operation modes mode pattern (communication bits) related data mode trailer m1 m0 c5 c4 c3 c2 c1 c0 register write 0 0 a5 a4 a3 a2 a1 a0 data byte (or more bytes in case of auto-incrementing) register read 0 0 a5 a4 a3 a2 a1 a0 fifo load 10000000 one or more bytes of fifo data fifo reset 10111111 directcommand mode 1 1 c5 c4 c3 c2 c1 c0 - functional overview ST25R3911B 34/129 docid029656 rev 2 figure 10. spi communication: writing a single byte figure 11. spi communication: writing multiple bytes reading data from addressable registers (read mode) after the spi operation mode bits the address of re gister to be read has to be provided from the msb to the lsb. then one or more data bytes are transferred to miso output, always from the msb to the lsb. as in case of the write mode also the read mode supports auto- incrementing address. mosi is sampled at the falling edge of sclk (like shown in th e following diagrams), data to be read from the ST25R3911B internal register is driven to miso pin on rising edge of sclk and is sampled by the master at the falling edge of sclk. in case the register on defined address d oes not exist all 0 data is sent to miso. figure 12 is an example for reading of single byte. 0 6 9 ' ; ; 6 6 6 & / . 0 2 6 , 7 z r o h d g l q j e l w v l q g l f d w h 0 r g h 6 & / . u l v l q j h g j h ' d w d w u d q v i h u u h g i u r p 0 & 8 6 & / . i d o o l q j h g j h ' d w d l v v d p s o h g ' d w d l v p r y h g w r d g g u h v v $ $ ! 5 d l v l q j h g j h l q g l f d w h v h q g r i : u l w h 0 r g h ' ' ' ' ' ' ' $ $ $ $ $ $ 0 6 9 6 6 u d l v l q j h g j h l q g l f d w h v h q g r i : u l w h p r g h 7 z r o h d g l q j v l q g l f d w h : u l w h p r g h 6 & / . i d o o l q j h g j h ' d w d p r y h g w r d g g u h v v $ $ ! $ $ $ $ $ $ ' ' ' ' ' ' ' ' ; ; ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 6 6 6 & / . 0 2 6 , 6 & / . i d o o l q j h g j h ' d w d p r y h g w r d g g u h v v $ $ ! 6 & / . i d o o l q j h g j h ' d w d p r y h g w r d g g u h v v $ $ ! q 6 & / . i d o o l q j h g j h ' d w d p r y h g w r d g g u h v v $ $ ! q docid029656 rev 2 35/129 ST25R3911B functional overview 71 figure 12. spi communication: reading a single byte loading transmitting data into fifo loading the transmitting data into the fifo is similar to writing data into an addressable registers. difference is that in case of loading more bytes all bytes go to the fifo. spi operation mode bits 10 indicate fifo operation s. in case of loading transmitting data into fifo all bits functional overview ST25R3911B 36/129 docid029656 rev 2 operation mode bits 10 indicate fifo operations. in case of reading the received data from the fifo all bits docid029656 rev 2 37/129 ST25R3911B functional overview 71 figure 15. spi communication: direct command direct command chaining as shown in figure 16 , direct commands with immediate execution can be followed by another spi mode (read, write or fifo) without deactivating the /ss signal in between. figure 16. spi communication: direct command chaining spi timing 0 6 9 6 & / . u l v l q j h g j h ' d w d w u d q v i h u u h g i u r p 0 & 8 6 & / . i d o o l q j h g j h ' d w d l v v d p s o h g 6 6 u d l v l q j h g j h l q g l f d w h v v w d u w r i f r p p d q g h [ h f x w l r q 7 z r o h d g l q j v l q g l f d w h & r p p d q g 0 r g h & ; ; 6 6 6 & / . 0 2 6 , & & & & & 0 6 9 6 6 ' l u h f w f r p p d q g 5 h d g : u l w h r u ) , ) 2 0 r g h table 7. spi timing symbol parameter min typ max unit comments general timing (v dd = v dd_io = v sp_d = 3.3 v, 25 c) t sclk sclk period 167 - - ns t sclk =t sclkl +t sclkh , use of shorter sclk period may lead to incorrect fifo operation. t sclkl sclk low 70 - 1 - t sclkh sclk high 70 - - - t ssh spi reset (/ss high) 100 - - - t ncsl /ss falling to sclk rising 25 - - first sclk pulse t ncsh sclk falling to /ss rising 300 - - last sclk pulse t dis data in set-up time 10 - - - t dih data in hold time 10 - - - functional overview ST25R3911B 38/129 docid029656 rev 2 figure 17. spi general timing figure 18. spi read timing interrupt interface there are three interrupt registers implemented in the ST25R3911B: main interrupt register contains information about six interrupt sour ces, while two bits re ference to interrupt read timing (v dd = v dd_io = v sp_d = 3.3 v, 25 c, c load 50 pf) t dod data out delay - 20 - ns - t dohz data out to high impedance delay -20- - table 7. spi timing (continued) symbol parameter min typ max unit comments 0 6 9 ' $ 7 $ , ' $ 7 $ , ' $ 7 $ , w 6 & / . + w 1 & 6 / w 6 & / . / w ' , 6 w ' , + w 1 & 6 + 6 6 0 2 6 , 0 , 6 2 6 & / . 0 6 9 ' $ 7 $ , ' $ 7 $ 2 ' $ 7 $ 2 w ' 2 ' w ' 2 + = 6 6 0 2 6 , 0 , 6 2 6 & / . docid029656 rev 2 39/129 ST25R3911B functional overview 71 sources detailed in timer and nfc interrupt register and error and wake-up interrupt register . when an interrupt condition is met the source of interrupt bit is set in the main interrupt register and the irq pin transitions to high. the microcontroller then reads the main interrupt register to distinguish between different interrupt sources. the interrupt registers 0x17, 0x18 and 0x19 are to be read in one attempt. after a particular interrupt register is read, its content is reset to 0. exceptions to this rule are the bits pointing to auxiliary registers. th ese bits are only cleared when corresponding auxiliary register is read. irq pin transitions to low after the interrupt bit(s) that caused its transition to high has (have) been read. note: there may be more than one interrupt bi t set in case the microcontroller does not immediately read the interrupt registers after the irq signal has been set and another event causing interrupt has occurred. in that case th e irq pin transitions to low after the last bit that caused in terrupt is read. if an interrupt from a certain source is no t required, it can be disabled by setting corresponding bit in the mask interrupt registers. when masking a given interrupt source the interrupt is not produced, but the source of interrupt bit is still set in interrupt registers. fifo water level and fifo status registers the ST25R3911B contains a 96 byte fifo. in case of transmitting the control logic shifts the data that was previously loaded by the external microcontroller to the framing block and further to the transmitter. during reception, the demodulated data is stored in the fifo and the external microcontroller can download received data at a later moment. transmit and receive capa bilities of the st25r391 1b are not limited by the fifo size due to a fifo water level interrupt system. during transmission an interrupt is sent ( irq due to fifo water level in the main interrupt register ) when the content of data in the fifo passes from (water level + 1) to water level and the complete transmit frame has not been loaded in the fifo yet. the external microcontroller can now add more data in the fifo. the same stands for the reception: when the number of received bytes passes from (water level - 1) to water level an interrupt is sent to inform the external controller that data has to be downloaded from fifo in order not to lose receive data due to fifo overflow. during transmission water level ir q is additionally set in case all transmission bytes have not been written in fifo yet and if number of bytes written into fifio is lower than water level. in this case an irq is sent when number of bytes in fifo drops below 4. note: fifo irq is not prod uced while spi is active in fifo lo ad or read mode. due to this the fifo loading/reading rate has to be higher th an tx/rx bit rate, once fifo loading/reading is finished the /ss pin has to be pulled to vdd (logic remains in fifo load/read mode as long as /ss remains low). in case controller knows that the receive data fr ame is smaller than the fifo size the water level interrupt does not have to be served. in such case the water level interrupt can be masked. table 8. irq output name signal signal level description irq digital output cmos interrupt output pin functional overview ST25R3911B 40/129 docid029656 rev 2 the external controller has to serve the fifo faster than data is transmitted or received. using sclk frequency that is at least double th an the actual receive or transmit bit rate is recommended. there are two settings of the fifo water leve l available for receive and transmit in the io configuration register 1 . after data reception is terminated the external microcontroller needs to know how much data is still stored in the fifo: th is information is available in the fifo status register 1 and fifo status register 2 that display number of bytes in the fifo that were not read out. fifo status register 1 can also be read while reception and transmission processes are active to get info about current number of byte s in fifo. in that case user has to take in account that rx/tx process is going on and that the number of data bytes in fifo may have already changed by the time the reading of register is finished. the fifo status register 2 additionally contains two bits that indicate that the fifo was not correctly served during reception or tran smission process (fifo overflow and fifo underflow). fifo overflow is set when too much data is wr itten in fifo. in case this bit is set during reception the external controller did not react on time on water level irq and more than 96 bytes were written in the fifo. the received data is of course corrupted in such a case. during transmission this means that controller has written more data than fifo size. the data to be transmitted was corrupted. fifo underflow is set when data was read from empty fifo. in case this bit is set during reception the external controller read more data than was actually received. during transmission this means that controller has failed to provide the quantity of data defined in number of transmitted bytes registers on time. pin mcu_clk pin mcu_clk may be used as clock source for the external microcontroller. depending on the operation mode either a lo w frequency clock (32 khz) from the rc oscillator or the clock signal derived from crystal oscillator is av ailable on pin mcu_clk. the mcu_clk output pin is controlled by bits out_c1, out_cl0 and lf_clk_off in the io configuration register 1 . bits out_cl enable the use of pin mcu_clk as clock source and define the division for the case the crystal oscillator is runn ing (13.56 mhz, 6.78 mhz and 3.39 mhz are available). bit lf_clk_off controls the use of lo w frequency clock (32 khz) in ca se the crystal oscillator is not running. by default configuration (defined at power-up) the 3.39 mhz clock is selected and the low frequency clock is enabled. in transparent mode (see section 1.2.22: stream mode and transparent mode ) the use of mcu_clk is mandatory since clock that is sy nchronous to the field carrier frequency is needed to implement receive and transmit framing in the external controller. the use of mcu_clk is recommended also for the case where the internal framing is used. using mcu_clk as the microcontroller clock source generates noise synchronous with the reader carrier frequency and is therefore filtered out by the receiver, while using some other incoherent clock source may produce noise that perturbs the reception. use of mcu_clk is also better for emc compliance. docid029656 rev 2 41/129 ST25R3911B functional overview 71 1.2.13 direct commands table 9. direct commands command code (hex) command comments command chaining interrupt after termination operation mode (1) c1 set default puts the ST25R3911B in default state (same as after power-up) no no all c2, c3 clear stops all activities and clears fifo yes no en c4 transmit with crc starts a transmit sequence using automatic crc generation yes no en, tx_en c5 transmit with crc starts a transmit sequence without automatic crc generation yes no en, tx_en c6 transmit reqa transmits reqa command (iso14443a mode only) yes no en, tx_en c7 transmit wupa transmits wupa command (iso14443a mode only) yes no en, tx_en c8 nfc initial field on performs initial rf collision avoidance and switch on the field yes yes en (2) c9 nfc response field on performs response rf collision avoidance and switch on the field yes yes en (2) ca nfc response field on with n=0 performs response rf collision avoidance with n=0 and switch on the field yes yes en (2) cb go to normal nfc mode accepted in nfcip-1 active communication bit rate detection mode yes no - cc analog preset presets rx and tx configuration based on state of mode definition register and bit rate definition register yes no all d0 mask receive data receive after this command is ignored yes no en, rx_en d1 unmask receive data receive data following this command is normally processed (this command has priority over internal mask receive timer) yes no en, rx_en d2 - not used -- - d3 measure amplitude amplitude of signal present on rfi inputs is measured, result is stored in a/d converter output register no yes en d4 squelch performs gain reduction based on the current noise level no no en, rx_en functional overview ST25R3911B 42/129 docid029656 rev 2 d5 reset rx gain clears the current squelch setting and loads the manual gain reduction from receiver configuration register 1 no no en d6 adjust regulators adjusts supply regulators according to the current supply voltage level no yes en (3) d7 calibrate modulation depth starts sequence that activates the tx, measures the modulation depth and adapts it to comply with the specified modulation depth no yes en d8 calibrate antenna starts the sequence to adjust parallel capacitances connected to trimx_y pins so that the antenna lc tank is in resonance no yes en d9 measure phase measurement of phase difference between the signal on rfo and rfi no yes en da clear rssi clears rssi bits and restarts the measurement yes no en dc transparent mode amplitude of signal present on rfi inputs is measured, result is stored in a/d converter output register no yes en dd calibrate capacitive sensor calibrates capacitive sensor no yes see note (4) de measure capacitance performs capacitor sensor measurement no yes see note (5) df measure power supply - no yes en e0 start general purpose timer -yesnoen e1 start wake-up timer - yes no all except wu e2 start mask receive timer - yes no see note (6) e3 start no-response timer - yes no en, rx_en fc test access enable /w to test registers yes no all other fx - reserved for test - - - other codes - not used - - - 1. defines the bits of the operation control register that have to be set in order to accept a particular command. 2. after termination of this command i_cat or i_cac irq is sent. table 9. direct commands (continued) command code (hex) command comments command chaining interrupt after termination operation mode (1) docid029656 rev 2 43/129 ST25R3911B functional overview 71 set default this direct command puts the ST25R3911B in th e same state as power-up initialization. all registers are initialized to the default state. the only exceptions are for io configuration register 1 , io configuration register 2 and operation control register (not affected by set default command) that are set to default state only at power-up. note: results of different calibration and adjust commands are also lost. this direct command is accepted in all operat ing modes. in case this command is sent while en (bit 7 of the operation control register ) is not set fifo and fifo status registers are not cleared. direct command chaining is not allowed since this command clears all registers. irq due to termination of direct command is not produced. clear this direct command stops all current activities (transmission or reception), clears fifo, clears fifo status registers an d stops all timers except wake-up timer (in case bit nrt_emv in the general purpose and no-response timer control register is set to one, the no-response timer is not stoppe d). it also clears collision an d interrupt regi sters. this command has to be sent first in a sequence preparing a transmission before writing data to be transmitted in fifo (except in case of direct commands transmit reqa and transmit wupa). this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is possible. irq due to termination of direct command is not produced. transmit commands all transmit commands (transmit with crc, transmit without crc, transmit reqa and transmit wupa) are accepted only in case the transmitter is enabled (bit tx_en is set). before sending commands transmit with crc and transmit without crc direct command clear has to be sent, fo llowed by definition of number of transmitted bytes and writing data to be transmitted in fifo. direct commands transmit reqa and transmit wupa are used to transmit iso14443a commands reqa and wupa respectively. sending command clear before these two commands is not necessary. the number of valid bits in the last byte must be set to zero (nbtx<2:0> in the number of transmitted bytes register 2 ) prior to executing transmit reqa or transmit wupa. direct command chaining is possible. 3. this command is not accepted in case the external definition of the regulated voltage is selected in the regulator voltage control register (bit reg_s is set to high). 4. accepted in all modes in case bit cs_mcal of the capacitive sensor control register is set to 0. it is recommended to execute this command in power-down mode. 5. accepted in all modes, it is recommended to execute this command in power-down mode. 6. accepted only in the initial nfc active target communication mode. functional overview ST25R3911B 44/129 docid029656 rev 2 irq due to termination of direct command is not produced. nfc field on commands these commands are used to perform the rf co llision avoidance and swit ch the field on in case no collision was detected. the collis ion avoidance threshold defined in the external field detector threshold register is used to observe the rf_in inputs and to determine whether there is some other device emitting the 13.56 mhz field, present close to the ST25R3911B antenna. in case collision is no t detected the reader field is switched on automatically (bit tx_en in the operation control register is set) and an irq with i_cat flag in timer and nfc interrupt register is sent after minimum guar d time defined by the nfcip- 1 standard to inform the controller that me ssage transmission using a transmit command can be initiated. in case a presence of external field is detected an irq with i_cac flag is sent. in such case a transmission cannot be performed, nfc fiel d on command has to be repeated as long as collision is not detected anymore. command nfc initial field on performs initial collision avoidance according to nfcip-1 standard ; number n is defined by bits nfc_n1 and nfc_n0 in auxiliary definition register . command nfc response field on performs response collis ion avoidance according to nfcip-1 standard; number n is defined by bits nfc_n1 and nfc_n0 in auxiliary definition register . command nfc response field on with n= 0 performs response collision avoidance where n is 0. implemented active delay time is on lower nf cip-1 specification limit, since the actual active delay time will also incl ude detection of the field deactivation , controller processing delay and sending the nfc field on command. this command is accepted in case en (bit 7 of the operation control register ) is set and both xtal oscillator frequen cy and amplitude are stable. figure 19. direct command nfc initial field on 0 6 9 7 , ' 7 7 , 5 ) * q [ 7 5 ) : 6 w d u w 5 ) r q 7 5 ) : docid029656 rev 2 45/129 ST25R3911B functional overview 71 figure 20. direct command nfc response field on go to normal nfc mode this command is used to transition from nfc target bit rate detection mode to normal mode. additionally it copies the content of the nfcip bit rate detection display register to the bit rate definition register and correctly sets the bit tr_am in the auxiliary definition register . analog preset this command is used to preset receiver and transmitter configuration based on state of mode definition register and bit rate definition register . in case of sub-carrier bit stream or bpsk bit stream mode, this command should not be used. th e list of configuration bits that are preset is given in table 11 . table 10. timing parameters of nfc field on commands symbol parameter value unit comments t idt initial delay time 4096 /fc nfc initial field on t rwf rf waiting time 512 - t irfg initial guard time >5 ms nfc initial field on t adt active delay time 768 /fc nfc response field on t arfg active guard time 1024 table 11. register preset bits bit bit name function address 02h: table 20: operation control register 5 rx_chn 1: one channel enabled nfcip-1 active communication (both initiator and target) 3tx_en 0: disable tx operation nfcip-1 active communication (both initiator and target) note : in case of any target mode or nfcip-1 initiator mode bit tx_en is set to 0 to disable transmitter in case it was enabled. in nfci p-1 mode the switching on of the tr ansmitter field is controlled by dedicated commands. address 05h: table 26: iso14443a and nfc 106kb/s settings register 5nfc_f0 1: adds sb (f0) and len byte during tx and skip sb (f0) byte during tx nfcip-1 active communicatio n (both initiator and target) 0 6 9 7 $ ' 7 7 $ 5 ) * q [ 7 5 ) : 6 w d u w 5 ) r q 7 5 ) : functional overview ST25R3911B 46/129 docid029656 rev 2 mask receive data and unmask receive data after the direct command mask receive data the signal rx_on that enables the rssi and agc operation of the receiver (see section 1.1.2: receiver ) is forced to low, processing of the receiver output by the receive data framing block is disabled. this command is useful to mask receiver and receive framing from processing the data when there is actually no input and only a noise would be processed (for exam ple in case where a transponder processing time after receiving a command from the reader is long). masking of receive is also possible using mask receive timer. actual masking is a logical or of the two mask receive processes. the direct command unmask receive data is enabling normal processing of the received data (signal rx_on is set high to enable the rssi and agc operation), the receive data framing block is enabled. a common use of this command is to enable again the receiver operation after it was masked by the command mask receive data. in case mask receive timer is running while command unmask receive data is rece ived, reception is enabled, mask receive timer is reset. address 09h: table 34: auxiliary definition register 5 tr_am tx modulation type (depends on mode definition and tx bit rate) 0: ook iso144443a, nfcip-1 106 kb/s (both initiator and target), nfc forum type 1 tag 1: am iso144443b, felica ? , nfcip-1 212 kb/s and 424 kb/s 4 en_fd enables external field detector with peer detection threshold 0: all modes except nfcip-1 active communication 1: nfcip-1 active communication (both initiator and target) address 0ah: table 35: receiver configuration register 1 7 ch_sel 0: enables am channel nfcip-1 active communication (both initiator and target) 6 amd_sel am demodulator select (depend on rx bit rate) 0: peak detector all rx bit rates equal or below fc/16 (848 kb/s) 1: mixer all vhbr rx bit rates (fc/8 and fc/4) 5lp2 low pass control (depends on mode definition and rx bit rate), see table 3: receiver filter selection and gain range 4lp1 3lp0 2h200 first and third stage zero setting (depends on mode definition and rx bit rate), see table 3: receiver filter selection and gain range 1 h80 0z12k address 0ch: table 37: receiver configuration register 3 1lim clips output of 1 st and 2 nd stage 0: all modes except nfcip-1 active communication 1: nfcip-1 active communication (both initiator and target) 0 rg_nfc forces gain reduction in 2 nd and 3 rd gain stage 0: all modes except nfcip-1 active communication 1: nfcip-1 active communication (both initiator and target) table 11. register preset bits (continued) bit bit name function docid029656 rev 2 47/129 ST25R3911B functional overview 71 the commands mask receive data and unmask receive data are only accepted when the receiver is enabled (bit rx_en is set). direct command chaining is possible. irq due to termination of direct command is not produced. measure amplitude this command measures the amplitude on the rfi inputs and stores the result in the a/d converter output register . when this command is executed the transmitter and amplitude detector are enabled, the output of the amplitude detector is multiplex ed to the a/d converter input (the a/d converter is in absolute mode). the amplitude detector conversion gain is 0.6 v inpp / v out . one lsb of the a/d converter output represents 13.02 mv pp on the rfi inputs. a 3 v pp signal (the maximum allowed level on each of the two rfi inputs), results in 1.8 v output dc voltage and will produce a value of 1110 0110b on the a/d converter output. duration time: 25 s max. this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is not possible. irq due to termination of direct command is produced after command execution is terminated. squelch this direct command is intended to avoid de modulation problems of transponders that produce a lot of noise during data processing. it can also be used in a noisy environment. the operation of this command is explained in squelch . duration time: 500 s max. this command is only accepted when the transmitter and the receiver are operating. command is actually executed on ly in case signal rx_on is low. direct command chaining is not possible. irq due to termination of direct command is not produced. reset rx gain this command initializes the ag c, squelch and rssi block. sending this command stops a squelch process in case it is going on, clears the current squelch setting and loads the manual gain reduction from receiver configuration register 4 . this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is possible. irq due to termination of direct command is not produced. adjust regulators when this command is sent the power supply level of v dd is measured in maximum load conditions and the regulated voltage reference is set 250 mv below this measured level to functional overview ST25R3911B 48/129 docid029656 rev 2 ensure maximum possible stable regulated supply (see section 1.2.11: power supply system ). the use of this comma nd increases the system pssr. at the beginning of executio n of the command, both the receiver and transmitter are switched on to have the maximum current consumption, and the regulators are set to their maximum regulated voltage (5.1 v in case of 5 v supply and 3.4 v in case of 3.3 v supply). after 300 s v sp_rf is compared to v dd , if is not at least 250 mv lower the regulator setting is reduced by one step (120 mv in case of 5 v supply and 100 mv in case of 3.3 v supply) and measurement is done after another 300 s. the procedure is repeated until v sp_rf drops at least 250 mv below v dd , or until the minimum regulated voltage (3.9 v in case of 5 v supply and 2.4 v in case of 3.3 v supply) is reached. duration time: 5 ms max. this command is accepted if en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. this command is not accepted when the external definition of the regulated voltage is selected in the regulator voltage control register (bit reg_s is set to h). direct command chaining is not possible. irq due to termination of direct command is produced after command execution is terminated. calibrate modulation depth starts a sequence that activates the transmission, measures the modulation depth and adapts it to comply with the modulation depth specified in the am modulation depth control register . when calibration procedure is finished result is displayed in the same register. refer to section 1.2.20: am modulation depth: definition and calibration for details about setting the am modulation depth and running this command. duration time: 275 s max. this command is accepted when en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is not possible. irq due to termination of direct command is produced after command execution is terminated. calibrate antenna sending this command starts a sequence that adjusts the parallel capacitances connected to trimx_y pins so that the antenna lc tank is in resonance. see section 1.2.21: antenna tuning for details. duration time: 250 s max. this command is accepted when en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. measure phase this command measures the phase difference between the signals on the rfo outputs and the signals on the rfi inputs and stores the result in the a/d converter output register . docid029656 rev 2 49/129 ST25R3911B functional overview 71 during execution of the direct command meas ure phase the transmitter and phase detector are enabled, the phase detector output is multip lexed on the input of a/ d converter, which is set in relative mode. si nce the a/d converter range is from 1/6 vsp_a to 5/6 vs p_a the actual phase detector range is from 30o to 150o. values below 30o result in ffh, while values above 150o result in 00h. one lsb of the a/d conversion output represents 0.13% of carrier frequency period (0.468). the result of a/d conversion is in case of 90o phase shift in the middle of range (1000 0000b or 0111 1111b). a value higher than 1000 0000b means that phase detector output voltage is higher than v sp_a /2, which corresponds to case with phase shift lower than 90o. in the opposite case, when the phase shift is higher than 90o, the result of a/d conversion is lo wer than 0111 1111b. for example, the phase difference of 135o shown in figure 7 results in 0.75 v sp_a , result stored in a/d converter is 31d (1fh). the phase measurement result can be calculating using the following formulas: ? 0o 30o: result = 255 (decimal) ? 30o < < 150o: angle (in o) = 30 + [(255 - u_angle) / 255) * 120] ? 150o 180o: result = 0 (decimal) duration time: 25 s max. this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is not possible. irq due to termination of direct command is produced after command execution is terminated. clear rssi the receiver automatically clears the rssi bits in the rssi display register and starts to measure the rssi of the received signal when the signal rx_on is asserted. since the rssi bits store peak value (p eak-hold type) the variations of the receiver input signal will not be followed (this may happen in case of long messages or test proc edures). the direct command clear rssi clears the rssi bits in the rssi display register , and the rssi measurement is restarted (in case , of course, rx_on is still high). this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is possible. irq due to termination of direct command is not produced. transparent mode enters in the transparent mode. the transparent mode is entered on the rising edge of signal /ss and is maintained as long as signal /ss is kept high. this command is accepted when en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. calibrate capacitive sensor this command calibrates th e capacitive sensor. see section 1.1.5: capacitive sensor for more details. duration time: 3 ms max. functional overview ST25R3911B 50/129 docid029656 rev 2 this command is executed in case capacitive sensor automatic calibration mode is set (all bits cs_mcal in the capacitive sensor control register are set to 0). in order to avoid interference with xtal oscillator and reader magnetic field, it is strong ly recommended to use this command in power-down mode only. direct command chaining is not possible. irq due to termination of direct command is produced after command execution is terminated. measure capacitance this command performs the capacitance measurement. see section 1.1.5: capacitive sensor for more details. duration time: 250 s max. in order to avoid interf erence with xtal oscillator and read er magnetic fiel d it is strongly recommended to use this command in power-down mode only. direct command chaining is not possible. irq due to termination of direct command is produced after command execution is terminated. measure power supply this command performs the power supply measurement. configuration bits mpsv1 and mpsv0 of the regulator voltage control register define which power supply is measured (vdd,vsp_a, vsp_d and vsp_rf can be measured). result of measur ement is stored in the a/d converter output register . during the measurement the selected supply i nput is connected to a 1/3 resistive divider, whose output is multiplexed to a/d converter in absolute mode. due to division by 3, one lsb represents 23.438 mv. duration time: 25 s max. this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is not possible. irq due to termination of direct command is produced after command execution is terminated. 1.2.14 start timers see section 1.2.7: timers on page 25 . 1.2.15 test access the ST25R3911B does not contain any dedicate d test pins. a direct command test access is used to enable rw access of test register s and entry in different test modes. pins csi and cso are used as test pins. docid029656 rev 2 51/129 ST25R3911B functional overview 71 test mode entry and access to test registers test registers are not part of normal spi register address space. after sending a direct command test access, test registers can be accessed using normal read/write register spi command. access to test registers is possible in a chained command sequence where first command test access is sent, followed by read/write access to test registers using auto increment feature. after spi interface reset (ss toggle) the content of te st registers is kept. test register are set to default state at pow er-up and by sending commands set default and clear test registers. table 12. analog test and observation register test address 01h: analog test and observation register - type: rw bit name default function comments 7 tana_7 0 - reserved 6 tana_6 0 - reserved 5 tana_5 0 - reserved 4 - 0 not used - 3 tana_3 0 see table 13 these test modes are also intended for observation in normal mode. other modes of this register are also available when analog test mode is not set. 2 tana_2 0 1 tana_1 0 0 tana_0 0 table 13. test access register - tana signal selection of csi and cso pins tana_ pin csi pin cso comments 3210type functionality type functionality 0001 ao analog output of am channel (before digitizer) do digital output of am channel (after digitizer) normal operation 0010 ao analog output of pm channel (before digitizer) do digital output of pm channel (after digitizer) normal operation 0011 ao analog output of am channel (before digitizer) ao analog output of pm channel (before digitizer) normal operation 0100do digital output of am channel (after digitizer) do digital output of pm channel (after digitizer) normal operation 01 01 ao analog signal after first stage ao analog signal after second stage normal operation: ? pm channel if enabled ? am if pm is not enabled 1001do channel selection from logic do collision avoidance detector output collision avoidance detectors are enabled 1010do digital tx modulation signal do select pm analog part of channel selection 0001 ao analog output of am channel (before digitizer) do digital output of am channel (after digitizer) normal operation functional overview ST25R3911B 52/129 docid029656 rev 2 1.2.16 power-up sequence at power-up, the ST25R3911B enters the power-down mode. the content of all registers is set to the default state. 1. the microcontroller, after a power-up, must correctly configure the two io configuration registers. the content of these two regist ers defines operation options related to hardware (power supply mode, xtal type, use of mcu_clk clock, antenna operation mode). 2. configure the regulators. it is recommended to use direct command adjust regulators to improve the system psrr. 3. when implementing the lc tank tuning, send the direct command calibrate antenna. 4. when using the am modulation (iso-14443b for example), set the modulation depth in the am modulation depth control register and send the command calibrate modulation depth. 5. the ST25R3911B is now ready to operate. 1.2.17 reader operation to begin with, the operation mode and data ra te have to be configured by writing the mode definition register and bit rate definition register . additionally, the receiver and transmitter operation options related to operation mode hav e to be defined. this is done automatically by sending the direct command analog preset. if more options are required apart from those defined by analog preset, then such opti ons must be additionally set by writing the appropriate registers. next, the ready mode has to be entered by setting the bit en of the operation control register . in this mode the oscillato r is started and the regula tors are enabled. when the oscillator operation is stab le, an interrupt is sent. before sending any command to a transponder, the transmitter and receiver have to be enabled by setting the bits rx_en and tx_en. rf id protocols usually require that the reader field is turned on for a while before sending th e first command (5 ms for iso14443). general purpose timer can be used to count this time. if reqa or wupa have to be sent, this is simply done by sending the appropriate direct command, otherwise the following sequence has to be followed: 1. send the direct command clear 2. define the number of transmitted bytes in the number of transmitted bytes register 1 and number of transmitted bytes register 2 3. write the bytes to be transmitted in the fifo 4. send the direct command transmit with crc or transmit withou t crc (whichever is appropriate) 5. when all the data is transmitted an interrup t is sent to inform the microcontroller that the transmission is finished (irq due to end of transmission) after the transmission is executed, the st25 r3911b receiver automatically starts to observe the rfi inputs to detect a transponder response. the rssi and agc (when enabled) start. the framing block processes the sub-carrier signal from receiver and fills the fifo with data. when the reception is finished and all the data is in the fifo an interrupt is sent to the microcontroller (irq due to end of receive), additionally the fifo status register 1 and fifo status register 2 display the number of bytes in the fifo so that the microcontroller can proceed with data download. docid029656 rev 2 53/129 ST25R3911B functional overview 71 in case of an error or bit co llision detected during reception, an interr upt with appropriate flag is sent. transmit and receive when the data packet is longer than fifo in case a data packet is longer than fifo the sequence explained above is modified. before transmit the fifo is filled. during transm it an interrupt is sent when remaining number of bytes is lower th an the water level (irq due to fifo water level). the microcontroller in turn adds more data in th e fifo. when all the da ta is transmitted an interrupt is sent to inform the microc ontroller that transmission is finished. during reception situation is similar. in case the fifo is loaded with more data than the receive water level, an interrupt is sent and the microcontr oller in turn read s the data from the fifo. when reception is finished an interrupt is s ent to the microcontroller (irq due to end of receive), additionally the fifo status register 1 and fifo status register 2 display the number of bytes in the fifo that are still to be read out. anticollision ? iso 14443a note: for this section, it is assumed that ther e is more than one iso/iec 14443a picc in the reader rf field, and all of them are comp atible with iso/iec 14443 up to level 4. this section describes the anticollision pr ocedure of ST25R3911B for iso14443a tags. after an iso14443 type a tag enters in the reader field, the reader has to perform a selection process that brings it into the pr otocol state in which the actual application implemented in the tag can be executed. this selection process is described in the iso/iec 14443-3. figure 21 shows the states that a tag and a reader have to pass through to enter the protocol state. the selection procedure starts when a picc enters the reader field and the pcd sends a reqa (or wupa) command followed by an anti collision procedure (i ncluding select, rats and pps). functional overview ST25R3911B 54/129 docid029656 rev 2 figure 21. iso14443a states for pcd and picc setting up the ST25R3911B for iso 14443a anticollision to set up the ST25R3911B fo r the iso14443a anticollision fo llow the steps indicated below. 1. the initiator operation mode of ST25R3911B must be set up for iso 14443a in the mode definition register (default is already for iso14443a). 2. the tx and rx bit rates must be set to default (106 kbps) in the bit rate definition register . 3. set the antcl bit in the iso14443a and nfc 106kb/s settings register . this needs to be set before sending the reqa (or wupa ). as a result, the ST25R3911B will not trigger a framing er ror if in case the collision occurs in the atqa or during anticollision procedure. note: this bit must be set to one for reqa, wupa and antocollision commands, for other commands it has to be zero. 4. review and set a value for mask receive timer register lower than the frame delay time, as required by the iso14443a., and set the no-response timer register 1 and no-response timer register 2 according to the requirements. this is typically larger than the fdt. 0 6 9 6 w d q g e \ 3 r o o i r u 3 , & & z l w k 5 ( 4 $ 5 h f h l y h $ 7 4 $ , q f u h d v h & d v f d g h o h y h o , 6 2 & k h f n 6 $ . 3 h u i r u p e l w i u d p h d q w l f r o o l v l r q o r r s 3 r z h u r i i q r i l h o g , 6 2 , g o h i l h o g 2 1 5 h d g \ $ f w l y h 3 , & & v w d w h v 3 & ' v w d w h v 8 , ' q r w f r p s o h w h 8 , ' f r p s o h w h d q g 3 , & & f r p s o l d q w z l w k , 6 2 docid029656 rev 2 55/129 ST25R3911B functional overview 71 note: ST25R3911B offers the resolution of n/2 (64/fc - half steps) compared to n (128/fc) as mentioned in iso 14443a so that the receiver can be unmasked n/2 steps before the actual transmission from the picc. 5. according to iso 14443a the fdt must be 1236/fc if last transmitted bit is 1, or 1172/fc if last transmitted bit is 0. figure 22 shows an example of how mrt and nrt timers are set for a given fdt. figure 22. selection of mrt and nrt for a given fdt 6. the receiver and transmitter operation options related to operation mode must be defined. this is done automatically by s ending the direct command analog preset. if different options are required apart from thos e defined by analog preset, they must be additionally set by writi ng the appropriate registers. 7. set rx_en and tx_en in the operation control register . rfid protocols usually require that the reader field is turned on for a while before sending the first command (5 ms for iso14443). general purpose timer ca n be used to count this time. 8. the reply from picc for the reqa, wupa , and replies within anticollision sequence before sak do not contain crc. in this case the no_crc_rx bit in the auxiliary definition register must be set to 1 (receive wi thout crc) before sending these commands. reqa and wupa sending these two commands is simple since they are implemented as direct commands (transmit reqa and transmit wupa). the end of transmission of these commands is signaled to microcontroller by an interrupt - irq due to end of transmission). after the transmission is executed, the ST25R3911B receiv er automatically starts to observe the rfi inputs to detect a transponder after the expiration of the mask receive timer. as a response to reqa (or wupa) all the picc in the field respond simultaneously with an atqa. a collision can occur in this state if th ere are picc with different uid size or has the bit frame anticollision bits set diff erently. hence it is important to set the antcl bit to 1. if there is any irq (except i_nre) that ST25R3911B sign als, the microcontroller must consider as a valid presence of tag and must proc eed with the anticollision procedure. if more than one picc is expected in the fiel d, the following algorithm must be used to select multiple tags: 0 6 9 3 & ' w r 3 , & & ) ' 7 0 5 7 ) ' 7 i f 1 5 ( ! ) ' 7 i f ? 3 , & & w r 3 & ' functional overview ST25R3911B 56/129 docid029656 rev 2 1. send reqa, if there is any answer continue 2. perform anticollision, and select one picc 3. send hlta to move the selected picc to the halt state 4. go to step 1, and repeat this procedure until all the piccs are in halt state and all the uids have been extracted. anticollision procedure after receiving the atqa from the tags in the field, the next step is to execute the anticollision procedur e to resolve the ids of the tags. the procedure mainly uses the anticoll ision and select commands, which consist of: ? select code sel (1 byte) ? number of valid bits nvb (1 byte) ? 0 to 40 data bits of uid cln according to the value of nvb the anticollision command uses bit oriented anticollision fr ame (it does not use crc). in this case the transmit needs to be done with direct command transmit without crc and for the receive, the no_crc_rx bit in the auxiliary definition register must be set to 1. the final select command and its response sak cont ains a crc, so the transmit needs to be done with command transmit with crc and before sending this command the configuration bit no_crc_rx bit in the auxiliary definition register must be set back to 0. if there is more than o ne picc in the field, the collision will occur when the tags reply to the anticollision command during anticollision, wh en the piccs reply back with their uid. this collision can occur after a co mplete byte (full byte scenari o) or it can occur within a byte (split byte scena rio). the antcl bit in iso14443a and nfc 106kb/s settings register must be set during this pr ocedure too. as a result, th e ST25R3911B will not trigger a framing error. this bit is also responsible for correct timing of anticollision and correct parity extraction. note: it must only be set before sending an anticollision frame, re qa or wupa. this bit must not be used in any other commands. figure 23 shows how to implement the anticollision with ST25R3911B. since spi is byte oriented, in case of split byte scenario, the invalid msb bits must be ignored when reading out the fifo for the received data. similarly, 0s must be concatenated as m sb bits to complete a byte for the transmit (which will then be ignored based on register 0x1e). docid029656 rev 2 57/129 ST25R3911B functional overview 71 figure 23. flowchart for iso14443a anticollision with ST25R3911B 1.2.18 felica ? reader mode the general recommendation from section 1.2.17: reader operation is valid for felica ? reader mode as well. both 212 and 424 kb/s bit rates are supported, they are same in both directions (reader to tag and tag to reader). modulation reader to tag is am. in felica ? mode the felica ? frame format (see figure 24 ) is supported. 0 6 9 & d v f d g h o h y h o q q ) l o o ) , ) 2 z l w k 6 ( / q 1 9 % [ 6 h w u h j l v w h u v 1 x p e h u r i w u d q v p l w w h g e \ w h v u h j l v w h u [ 1 x p e h u r i w u d q v p l w w h g e \ w h v u h j l v w h u [ 6 h q g f r p p d q g 7 u d q v p l w z l w k r x w & 5 & ( [ s h f w h g l q w h u u x s w v , b w [ h , b f r o l i f r o o l v l r q r f f x u v , b u [ v , b u [ h 6 ( / q [ i r u q i r u e \ w h v 8 , ' 6 ( / q [ i r u q i r u e \ w h v 8 , ' 6 ( / q [ i r u q i r u e \ w h v 8 , ' 5 h d g ) , ) 2 i r u w k h y d o l g g d w d i u r p w k h v h o h f w h g 3 , & & , b f r o r f f x u h g " 6 h w q r b & 5 & b u [ d q w f o 5 h d g & r o o l v l r q ' l v s o d \ 5 h j l v w h u w r l g h q w l i \ w k h e l w s r v l w l r q z k h u h w k h f r o o l v l r q r f f x u u h g 5 h d g ) , ) 2 i r u w k h u h v s r q v h i u r p 3 , & & ) l o o ) , ) 2 z l w k s d u w r i e l w d q w l f r o o l v l r q i u d p h 6 ( / q 1 9 % d y d l o d e o h i u r p y d o l g w d j u h v s r q v h u h f h l y h g y d o l g g d w d r u i r u w k h e l w z k h u h w k h f r o o l v l r q r f f x u u h g 6 h w u h j l v w h u v p h q w l r q w k h q x p e h u r i u h f h l y h g i x o o e \ w h v d q g v s o l w e l w v l q 1 x p e h u r i w u d q v p l w w h g e \ w h v u h j l v w h u 1 x p e h u r i i x o o e \ w h v 1 x p e h u r i w u d q v p l w w h g e \ w h v u h j l v w h u 6 h w q r b & 5 & b u [ d q w f o 6 h q g f r p p d q g 7 u d q v p l w z l w k & 5 & ( [ s h f w h g q w h u u x s w v , b w [ h , b u [ h 6 h q g 6 ( / ( & 7 i l o o ) , ) 2 z l w k 6 ( / q 1 9 % [ 8 , ' & / q 8 , ' f r p s o h w h " ( q g d q w l f r o o l v l r q z l w k 5 $ 7 6 ( q w h u & d v f d g h o h y h o q < h v < h v 1 r 1 r ) , ) 2 l v i l o o h g l q z l w k 3 , & & u h v s r q v h ) , ) 2 l v i l o o h g l q z l w k 3 , & & u h v s r q v h ) , ) 2 l v i l o o h g l q z l w k 6 $ . 3 , & & v h q g v f r p s o h w h 8 , ' functional overview ST25R3911B 58/129 docid029656 rev 2 figure 24. felica ? frame format felica ? transmission in order to transmit felica ? frame only the payload data is put in the fifo. the number of payload bytes is defined in the number of transmitted bytes register 1 and number of transmitted bytes register 2 . preamble length is defined by bits f_p1 and f_p0 in the iso14443b and felica settings register , default value is 48 bits , but other options are possible. transmission is triggered by sending direct command transmit with crc. first preamble is sent, followed by sync and length bytes. then payload stored in fifo is sent, transmission is terminated by two crc bytes that are calculated by the ST25R3911B. length byte is calculated from ?number of transmitted bytes?. the following equation is used: length = payload length + 1 = number of transmitted bytes +1 felica ? reception after transmission is done the ST25R3911B logic starts to parse the receiver output to detect the preamble of felica ? tag reply. once the preamble (followed by the two sy nc bytes) is detected the length byte and payload data are put in the fifo. crc bytes are internally checked. 1.2.19 nfcip-1 operation the ST25R3911B supports all nfcip-1 initia tor modes and active communication target modes. all nfcip-1 bit rates (106, 212 and 424 kbit/s) are supported. nfcip-1 passive communication initiator nfcip-1 passive communication is equiva lent to reader (pcd) to tag (picc) communication where initiator acts as a reader and target acts as tag. the only difference is that in case of the nfcip-1 passive communicati on the initiator performs initial rf collision avoidance procedure at the beginning of communication. in order to act as nfcip-1 passive communication initiator the ST25R3911B has to be configured according to table 14 . preamble: 48 data bits all logical 0 sync: 2 bytes (b2h, 4dh) length: length byte (value= payload l ength + 1), the length range is from 2 to 255 payload: payload crc: 2 bytes preamble sync length payload crc docid029656 rev 2 59/129 ST25R3911B functional overview 71 initial set-up of the operation control register before the start of communication is the same as in case of reader to tag communicati on, with the exception that the transmitter is not enabled by setting the tx_en bit. the dire ct command nfc initial field on is sent instead. this command first pe rforms the initial rf collision avoidance with collision avoidance threshold defined in the external field detector threshold register . the timing of collision avoidance is according to nfcip-1 standard (for timing details see table 10: timing parameters of nfc field on commands ). in case collision is no t detected the tx_en bit is automatically set to switch the transm itter on. after minimum guard time t irfg the i_cat irq is sent to inform controller that th e first initiator command can be sent. from this point on communication is the same as for iso14443a (for 106 kb/s) or for felica ? (for 242 and 424 kb/s) reader communication. in case a presence of external field is de tected an i_cac irq is sent. in such case a transmission should not be performed, command nfc initial field on has to be repeated until collision is not detected anymore. initial collision avoidance is no t limited to modes su pported by nfcip-1. the initial collision avoidance according to procedure described above can be performed before any reader mode is started to avoid collision with an hf re ader or an nfc device ope rating in proximity. support of nfcip-1 transport frame format figure 25 shows the transport frame according to nfcip-1. figure 25. transport frame format according to nfcip-1 transport frame for bit rate 212 and 424 kb/s has the same format as communication frame used during initialization and sdd. this format is al so used in felica ? protocol (see also section 1.2.18: felica? reader mode ). in case of 106 kb/s the sb (start byte at f0h) and len (length byte) are only used in transport frame. support of transport frame for 106 kb/s nfcip-1 communication is enabled by setting bit nfc_f0 in the iso14443a and nfc 106kb/s settings register . table 14. operation mode/bit rate setting for nfcip-1 passive communication nfcip-1 bit rate (kb/s) operation mode setting bit rate for tx (kb/s) bit rate for rx (kb/s) comments 106 iso14443a fc/128 (~106) fc/128 (~106) - 212 felica ? fc/64 (~212) - in felica mode data rate is the same in both directions 424 fc/32 (~424) - sb len cmd0 cmd1 byte 0 byte 1 byte 2 ? ? byte n e1 sb len cmd0 cmd1 byte 0 byte 1 byte 2 ? ? byte n e2 pa transport data field transport data field frame format for 106 kbps frame format for 212 kbps and 424 kbps functional overview ST25R3911B 60/129 docid029656 rev 2 once this bit is set and iso 14443a mode with bit rate 106 kb/s is configured, the ST25R3911B behaves as indicated in the next subsections. transmission in order to transmit a transport frame only the transport data has to be put in fifo. the number of transport data bytes is defined in the number of transmitted bytes register 1 and number of transmitted bytes register 2 . transmission is triggered by sending direct command transmit with crc. first start byte with value f0h followed by length byte are sent. then transport da ta stored in fifo is sent, tran smission is terminated by two crc bytes (e1 in figure 25 ) that are calculated by the st25r39 11b. length byte is calculated from ?number of transmitted bytes?. the following equation is used: length = transport data length + 1 = number of transmitted bytes +1 reception after transmission is done the ST25R3911B logic starts to parse the receiver output to detect the start of tag reply. once the start of communication sequence is de tected the first byte (start byte with value f0h) is checked the length byte and trans port data bytes are put in the fifo. crc bytes are internally checked. in case the start byte is not equal to f0h the following data bytes are still put in fifo, additionally a so ft framing error irq is set to indicate the start byte error. nfcip-1 active communication initiator during nfcip-1 active communica tion both, initiator and target switch on its field when transmitting and switch off its field when receiv ing. in order to operate as nfcip-1 active communication initiator the ST25R3911B has to be configured according to table 15 (bit targ in mode definition register has to be 0): after selecting the nfcip-1 active communication mode the receiver and transmitter have to be configured properly. this configuratio n can be done automatically by sending direct command analog preset (see analog preset ). during nfcip-1 active communication the rf collision avoidance and switching on the field is performed using nfc field on commands (see nfc field on commands ), while the sending of message is performed using transmit commands as in the case of reader communication. alternatively the response rf collision avoidance sequence is started automatically when the switching off of target fi eld is detected in case the bit nfc_ar in the mode definition register is set. when nfcip-1 mode is activat ed the external field detector is automatically enabled by setting bit en_fd in the auxiliary display register . the peer detection threshold is used to table 15. operation mode/bit rate setting for nfcip-1 active communication initiator nfcip-1 bit rate (kb/s) initiator operation mode setting bit rate for tx (kb/s) bit rate for rx (kb/s) comments 106 nfcip-1 active communication fc/128 (~106) - data rate is the same in both directions for all nfcip-1 communication. 212 fc/64 (~212) - 424 fc/32 (~424) - docid029656 rev 2 61/129 ST25R3911B functional overview 71 detect target field. during execution of ?nfc field on? commands, the collision avoidance threshold is used. initial set-up of the operation control register before the start of communication is the same as in case of reader to tag communicati on with the exception that the transmitter is not enabled by setting the tx_en bit. the tx_en bit and therefore switching on of the transmitter is controlled by nfc field on commands. switch ing off the field is performed automatically after a message has been sent. the general purpose and no-response timer control register is used to define the time during which the field stays switched on after a message has been transmitted. in order to receive the nfcip-1 active reply only the am demodulation channel is used. due to this the receiver am channel has to be enabled. the preset done by analog preset command enables only the am demodulation channel, while pm channel is disabled to save current. in nfcip-1 active communication the nfcip-1transport frame format (see figure 25 ) is always used. due to this the iso14443a and nfc 106kb/s settings register bit nfc_f0 is set by analog preset command (see support of nfcip-1 transport frame format ). nfcip-1 active communication sequence when bit nfc_ar in the mode definition register is set (automatic response rf collision avoi dance sequence). during this sequence bits nfc_n1 and nfc_n0 of the auxiliary definition register have to be 0 to produce response collision avoidance sequence with n=0: 1. the direct command nfc initial field on is sent. in case no collision was detected during rf collision avoidance t he field is switched on and an irq with i_cat flag set is sent to controller after t irfg . 2. the message, prepared as in case of read er to tag communication, is transmitted using transmit command. 3. after the message is sent the field is s witched off. the time between the end of the message and switching off the field is de fined by the general purpose timer (the general purpose timer irq may be masked since controller does not need this information). 4. after switching off its field the ST25R3911B starts the no-response timer and observes the external field detector output to detect the switching on of the target field. in case the target field is not dete cted before no-response timer timeout, an irq due no-response timer expire is sent. 5. when target field is detected an irq with i_eon flag set is sent to controller and mask receive timer is started. after the mask re ceive timer expires the receiver output starts to be observed to detect start of the target response. the reception process goes on as in case of reader to tag communication. 6. when the external field detector detects th at the target has switched off its field, it sends an irq with i_eof flag set to the controller, and in case bit nfc_ar is set automatically activates the sequence of direct command nfc response field on. in case no collision is detected du ring rf collision avoidance t he field is switched on and an irq with i_cat flag set is sent to controller after t arfg . 7. sequence loops through point 2. in case the last initiator comma nd is sent in next sequence (dls_req in case of nfcip-1 protocol) the bit nfc_ar in the mode definition register has to be put to 0 to avoid switching on the initiator field after the target has switched of its field. functional overview ST25R3911B 62/129 docid029656 rev 2 nfcip-1 active communication target the ST25R3911B target mode is activated by setting bit targ in the mode definition register to 1. when target mode is ac tivated the external field detect or is automatically enabled by setting bit en_fd in the auxiliary definition register . when bit targ is set and all bits of the operation control register are set to 0, the ST25R3911B is in low power initial nfc target mode. in this mode the external field detector with peer detection threshold is enabled. there are two different nfc target modes implemented (defined by mode bits of the mode definition register ): the bit rate detection mode and normal mode. in the bit rate detection mode the framing logic performs automatic detecti on of the initiator data rate and writes it in the nfcip bit rate detection display register . in the normal mode it is supposed that the data rate defined in the bit rate definition register is used. after selecting the nfcip-1 active target mode the receiver and transmitter have to be configured properly. configuration is the same as in case of nfcip-1 active initiator mode. this configuration can be done automatically by sending direct command analog preset (see analog preset). nfcip-1 active communication sequence when bit nfc_ar in the mode definition register is set (automatic response rf collision avoi dance sequence). during this sequence bits nfc_n1 and nfc_n0 of the auxiliary definition register have to be 0 to produce response collision avoidance with n=0. the following sequence assumes that the st25 r3911b is in the low power initial nfc target mode with the bit rate detectio n mode selected. bit nfc_ar in the mode definition register is set (automatic response rf collision avoidance sequ ence). when the initiator field is detected the following sequence is executed: 1. an irq with i_eon flag set is sent to the controller. 2. the controller turns on the oscillator, regulator and rece iver. mask receive timer is started by sending direct command start mask receive timer timer. after the mask receive timer expires the receiver output starts to be observed to detect start of the initiator message. 3. once the start of initiator message is dete cted, an irq due to start of receive is sent, the framing logic switches on a module that automatically recognizes the bit rate of signal sent by the initiator. once the bit rate is recognized an irq with i_nfct flag set is sent and the bit rate is automatically loaded in the nfcip bit rate detection display register . detection of bit rate is also a condit ion that automatic re sponse rf collision avoidance sequence is enabled). the received message is decoded and put into the fifo, irq is sent as after any received message. 4. the controller sends direct command go to normal nfc mode, to copy the content of the nfcip bit rate detection display register to the bit rate definition register and to change the nfcip-1 target mode to normal (the command go to normal mode and reading of received data can be chained). si nce the tx modulation type depends on bit rate, the tx modulation type also has to be correctly set at this point. 5. when the external field detector detects th at the target has switched off its field, it sends an irq with i_eof flag set to the controller, and in case bit nfc_ar is set automatically activates the sequence of di rect command nfc response field on. bits nfc_n1 and nfc_n0 of the auxiliary definition register are used to define number n of response rf collision avoidanc e sequence. in case no collis ion is detected during rf docid029656 rev 2 63/129 ST25R3911B functional overview 71 collision avoidance the field is switched on and an irq with i_cat flag set is sent to controller after t arfg . 6. the reply, prepared as in case of reader to tag communication is transmitted using transmit command. 7. after the message is sent the field is s witched off. the time between the end of the message and switching off the field is de fined in the general purpose timer (the general purpose timer irq may be masked since controller does not need this information). from this point on the communication with initiator loops through the following sequence (during this sequence bits nfc_n1 and nfc_n0 of the auxiliary definition register have to be 0 to produce response rf co llision avoidance with n=0): 1. after switching off its field the ST25R3911B starts the no-response timer and observes the external field detector output to detect the switching on of the initiator field. in case the initiator field is not de tected before no-respon se timer timeout, an irq due no-response timer expire is sent. 2. when initiator field is detected an irq with i_eon flag set is sent to controller and mask receive timer is started. after the mask re ceive timer expires the receiver output starts to be observed to detect start of the initiator response. the reception process goes on as in case of reader to tag communication. 3. when the external field detector detects th at the target has switched off its field, it sends an irq with i_eof flag set to the controller, and in case bit nfc_ar is set automatically activates the sequence of direct command nfc response field on. in case no collision is detected du ring rf collision avoidance t he field is switched on and an irq with i_cat flag set is sent to controller after t arfg. 4. the reply that was prepared as in case of reader to tag communication is transmitted using transmit command 5. after the message is sent the field is s witched off. the time between the end of the message and switching off the field is defined in general purpose timer. in case a new command from initiator is expected the general purpose timer irq may be masked since controller does not need this information. 6. in case a new command from initiator is expected the sequence loops through point 1. in case the target reply was the last in a sequence (dls_res in case of nfcip-1 protocol) a new command from initiator is not expected. at the moment the field is switched off, a general purpose timer irq is received and the ST25R3911B is put back in the low pow er nfc target mode by deactivating the operation control register . nfc mode is changed back to rate detection mode by writing the mode definition register . 1.2.20 am modulation depth: definition and calibration the ST25R3911B transmitter supports ook and am modulation. the choice between ook and am modulati on is done by writing bit tr_am in the auxiliary definition register . am modulation is preset by direct command analog preset in case the following protocols are configured: ? iso14443b ? felica ? ? nfcip-1 212 and 424 kb/s functional overview ST25R3911B 64/129 docid029656 rev 2 the am modulation depth can be automatically adjusted by setting the am modulation depth control register and sending the direct command calibrate modulation depth. there is also an alternative possib ility where the command calibrate mo dulation depth is not used and the modulated level is defined by writing the antenna driver rfo am modulated level definition register . am modulation depth definition using the direct command calibrate modulation depth before sending the direct command calibrate modulation depth the am modulation depth control register has to be configured in the following way: ? bit 7 (am_s) has to be set to 0 to choose definition by the command calibrate modulation depth ? bits 6 to 1 (mod5 to mod0) define target am modulation depth definition of modulation depth using bits mod5 to mod0 the rfid standard documents usually define the am modulation level in form of the modulation index. the modulation index is defined as (a-b)/(a+b), where a and b are, respectively, the amplitude of the non-modulated carrier and of the modulated carrier. the modulation index specification is differ ent for different standards. the iso-14443b modulation index is typically 10% with allowed range from 8 to 14%, while range from 10 to 30% is defined in the iso-15693, and 8 to 30% in the felica? and nfcip-1 212 kb/s and 424 kb/s. the bits mod5 to mod0 are used to calculate th e amplitude of the modulated level. the non- modulated level that was before measured by the a/d converter and stored in an 8 bit register is divided by a binary number in rang e from 1 to 1.98. bits mod5 to mod0 define binary decimals of this number. example in case of the modulation index 10% the modulated level amplitude is 1.2222 times lower than the non-modulated level. 1.2222 converted to binary and truncated to 6 decimals is 1.001110. so in order to define the modulation index 10% the bits mod5 to mod0 have to be set to 001110. table 16 shows setting of the mod bits for some often used modulation indexes. table 16. setting mod bits modulation index (%) a/b (dec) a/b (bin) mod5 ? mod0 8 1.1739 1.001011 001011 10 1.2222 1.001110 001110 14 1.3256 1.010100 010100 20 1.5000 1.100000 100000 30 1.8571 1.110111 110111 33 1.9843 1.111111 111111 docid029656 rev 2 65/129 ST25R3911B functional overview 71 execution of direct command calibrate modulation depth the modulation level is adjusted by increasing the rfo1 and rfo2 driver output resistance. the rfo drivers are composed of 8 binary weighted segments. usually all these segments are turned on to defi ne the normal, non-modulated leve l, there is also a possibility to increase the output resistance of the non-modulated state by writing the rfo normal level definition register . before sending the direct command calibrate modulation depth the oscillator and regulators have to be turned on. when the direct command calibrate modulation depth is sent the following procedure is executed: 1. the transmitter is turned on, non-modulated level is established. 2. the amplitude of the non-modulated carrier level established on the inputs rfi1 and rfi2 is measured by the a/d converter and stored in the a/d converter output register . 3. based on the measurement of the non-modulated level and the target modulated level defined by the bits mod5 to mod0 the target modulated level is calculated. 4. the output driver strength is adjusted using a successive approximation algorithm until the field strength is as clos e as possible to the calculated target modulated level. 5. the result of the output driver strength adjustment is copied in the am modulation depth display register . content of this register is used to define the am modulated level. note: after the calibration procedure is finished, the content of the rfo normal level definition register should not be changed. modifications of the content of this register will change the non-modulated amplitude and therefore the ratio between the modulated and non- modulated level. note: in case the calibration of antenna resona nt frequency in used, the command calibrate antenna has to be run before am modulation depth adjustment. am modulation depth definition using the rfo am modulated level definition register when bit 7 (am_s) of the am modulation depth control register is set to 1 the am modulated level is cont rolled by writing the rfo normal level definition register . if the setting of the modulated level is already known it is not necessary to run the calibration procedure, the modulated level can be def ined just by writing this register. it is also possible to implement calibration procedure through an external controller using the rfo normal level definition register and the direct command measure amplitude. this procedure has to be used when the target modulation depth is deeper than 33%. the procedure is the following: 1. write the non-modulated level in the rfo normal level definition register (usually it is all 0 to have the lower po ssible output resistance). 2. switch on the transmitter. 3. send the direct command measure amplitude. read result from the a/d converter output register . 4. calculate the target modulated level from th e target modulation index and result of the previous point. 5. in the following iterations content of the rfo normal level definition register is modified, the command measure amplitude ex ecuted and the result compared with the functional overview ST25R3911B 66/129 docid029656 rev 2 target modulated level as long as the result is not equal (or as close as possible) to the target modulated level. 6. at the end the content of the rfo normal level definition register that results in the target modulated leve l is written in the rfo am modulated level definition register while the rfo normal level definition register is restored with the non-modulated definition value. 1.2.21 antenna tuning the ST25R3911B integrates the blocks needed to check and to adjust the antenna lc tank resonance frequency. the phase and amplitude detector block is used for resonance frequency checking and adjustment. in order to implement the antenna lc tank calibration tuning capacitors have to be connected between the two coil terminals to th e pins trim1_3 to trim1_0 and trim2_3 to trim2_0. in case single driver is used only the pins trim1_3 to trim1_0 are used, pins trim2_3 to trim2_0 are left open. figure 26 shows the connection of the trim capacitors for both single (left side) and differential (right side) driving for the simple case where the antenna lc tank is direct ly connected to rfo pins. the trimx_y pins contain the hvnm os switching transistors to vss. the on resistance of trim1_0 and trim2_0 switch transistors to be connected to lsb tuning capacitor is 50 ? typ. at 3 v vsp_d, the on resist ance of other pins is binary weighted (the on resistance of trim1_3 and trim2_3 is 6.25 ? typ.) the breakdown voltage of the hvnmos switch transistors is 25 v, putting a limit to the maximum peak to peak voltage on lc tank in case tuning is used. during tuning procedure the resonance freque ncy is adjusted by connecting some of the tuning capacitors to vss and leaving others floating. the switches of the same binary weight are driven from the same source and are both on or off (the switches trim1_2 and trim2_2 are for example both either on or off). antenna tuning can be automatically performed by sending direct command calibrate antenna or by an algorithm implemented in external controller by performing phase and amplitude measurements and cont rolling the trim switches using antenna calibration control register . docid029656 rev 2 67/129 ST25R3911B functional overview 71 figure 26. connection of tuning capacitors to the antenna lc tank antenna tuning using calibrate antenna direct command in order to perform the antenna lc tank using direct command calibrate antenna binary weighted tuning capacitors have to be connec ted between the two coil terminals to the pins trim1_3 to trim1_0 and trim2_3 to trim2_0. during automatic procedure, started by sending the direct command calibrate antenna, the ST25R3911B finds the position of trim switches where the phase difference between the rfo output signal and rfi input signal is as clos e as possible to the target phase defined in the antenna calibration target register . in case the antenna lc tank is directly connected to rfo pins (see figure 26 , where the cases of single and differential driving are repor ted, respectively on the left and on the right) there is 90 phase shift between signal on the rfo outputs and the voltage on the rfi inputs when antenna lc tank is in resonance. in case additional emc filter is inserted between rfo outputs and antenna lc tank the phase shift in case of resonance depends on additional phase shift generated by emc filter. during execution of the direct command calibrate antenna the ST25R3911B runs several phase measurements and changes configuration of trimx_y pins in order to find the best possible setting. due to this the format of the antenna calibration target register is the same as the format of direct command measure phase result. the trimx_y pin configuration that is the resu lt of the direct command calibrate antenna can be observed by reading the antenna calibration display register . this register also contains an error flag that is set in case the tuning to target phase was not possible. after the execution of direct command calibra te antenna the actual phase can be checked by sending direct command measure phase. 0 6 9 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 5 ) 5 ) 5 ) , 5 ) , 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b $ q w h q q d f r l o 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 5 ) 5 ) 5 ) , 5 ) , 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b $ q w h q q d f r l o functional overview ST25R3911B 68/129 docid029656 rev 2 antenna tuning using antenna calibration control register there is also a possibility to control the position of the tr im switches by writing the antenna calibration control register . when the bit trim_s of this register is set to 1 position of the trim switches is controlled by bits tre_3 to tre_0. using this register and performing phase and amplitude measurements (using direct commands measure phase and measure amplitude) different tuning algorithms can be implemented in the external controller. 1.2.22 stream mode and transparent mode standard and custom 13.56 mhz rfid reader protocols not supported by the ST25R3911B framing can be implemented using the ST25R3911B afe and framing implemented in the external microcontroller. transparent mode after sending the direct command transparent mode the external microcontroller directly controls the transmission modulator and gets the receiver output (control logic becomes ?transparent?). the transparent mode is entered on rising edg e of signal /ss after sending the command transparent mode and is maintained as long as the signal /ss is kept high. before sending the direct command transparent mode the transmitter and receiver have to be turned on, the afe has to be configured properly. while the ST25R3911B is in the transparent mode, the afe is controlled directly through the spi: ? transmitter modulation is controlled by pin mosi (high is modulator on) ? signal rx_on is controlled by pin sclk (high enables rssi and agc) ? output of receiver am demodulation chain (dig itized sub-carrier signal) is sent to pin miso ? output of receiver pm demodulation chain (dig itized sub-carrier signal) is sent to pin irq by controlling the rx_on advanced receiver f eatures like the rssi and agc can be used. the receiver channel selection bits are valid also in transparent mode, therefore it is possible to use only one of the two channel outpu ts. in case single channel is selected it is always multiplexed to miso, while irq is kept low. configuration bits related to the iso mo de, framing and fifo are meaningless in transparent mode, while all other configuration bits are respected. use of transparent mode to implement active peer to peer (nfc) communication the framing implemented in the ST25R3911B supports all active modes according to the nfcip-1 specification (iso/iec 18092:2004). in case any amendments to this specification or some custom active nfc communication need to be implemented transparent mode can be used. there is no special nfc active communicati on transparent mode, controlling of the tx modulation and the rx is done as described above. the difference comparing to the reader docid029656 rev 2 69/129 ST25R3911B functional overview 71 transparent mode is that the em ission of the carrier field has to be enabled only during tx. this is done by writing the operation control register before and after tx. since with every spi command the transparent mode is lost it has to be re-entered. in order to receive the reply in active nf c communication mode only the am demodulation channel is used. due to this the receiver am channel has to be enabled, while pm can be disabled. implementing active communication requires detecti on of external field. setting the bit en_fd in the auxiliary definition register enables the external field de tector with peer detection threshold. when bit en_fd is selected and t he ST25R3911B is in transparent mode, the external field detector output is multiplexed to pin irq. this enables detection of external target/initiator field and perf orming rf collision avoidance. in case timing of the nfc field on command is correct for the nfc active protocol being implemented, these commands can be used in combination with the transparent mode. these commands are used to perform the rf co llision avoidance, switching on the field and timing out the minimum time from switching on th e field to start of transmitting the message. after getting the interrupt, the controller generates the message in the transparent mode. when bit en_fd is set and all bits of the operation control register are set to 0 the ST25R3911B is in the low power nfc target mode (same as in case of setting of targ bit, (see nfcip-1 active communication target). in this mode initiato r field is detected. after getting an irq with i_eon flag set, the c ontroller turns on the os cillator, regulator and receiver and performs reception in the transparent mode. mifare? classic compatibility for communication with mifare? classic complia nt devices the bit6 and bit7 from the register 05h can be used to enable type a custom frames. alternatively, the stream mode of ST25R3911B can be used to send and receive mifare? classic compliant or custom frames. stream mode stream mode can be used to implement protocols, where the low level framing needed for iso14443 receive coding can be used and dec oded information can be put in fifo. the main advantage of this mode over the transpar ent mode is that timing is generated in the ST25R3911B therefore the external controller does not have to operate in real time. the stream mode is selected in the mode definition register , the operating options are defined in the stream mode definition register . two different modes are supported for tag to reader comm unication (sub-carrier and bpsk stream modes). general rule for stream mode is that the first bit sent/received is put on the lsb position of the fifo byte. after selecting the stream mode the receiver and transmitter have to be configured properly (analog preset direct command doesn't apply for stream mode). sub-carrier stream mode this mode supports protocols where during the tag to reader communication the time periods with sub-carrier signal are interchanged with time periods without modulation (like in the iso14443a 106 kbit/s mode). in this mode the sub-carrier frequency and number of sub-carrier frequency periods in one reporting period is defined. sub-carrier frequency in the range from fc/64 (212 khz) to fc/8 (1695 khz) are supported. functional overview ST25R3911B 70/129 docid029656 rev 2 supported number of sub-carrier frequency periods in one reporting period range from two to eight. start of receive interrupt is sent and the first da ta bit is put in fifo after the first reporting time period with sub-carrier is detected. one bi t of fifo data gives information about status of input signal during one reporting period. l ogic 1 means that the sub-carrier was detected during reporting period, while 0 means that no modulation was detected during reporting period. end of receive is reported when no su b-carrier signal in more than eight reporting periods have been detected. figure 27 shows an example for setting scf = 01b and scp = 10b. with this setting the sub-carrier frequency is set to fc/32 (424 khz) and the reporting period to four sub-carrier periods (128/fc ~106 s). figure 27. example of sub-carrier stream mode for scf = 01b and scp = 10b bpsk stream mode this mode supports protocols where during the tag to reader communication bpsk code is used (like in the iso14443b mode). in this mode the sub-carrier frequency and number of sub-carrier frequency periods in one reporting period is defined. sub-carrier frequency in the range from fc/16 (848 khz) to fc/4 (3390 khz) are supported. supported number of sub-carrier frequency periods in one reporting period range from one to eight. start of receive interrupt is sent and the first da ta bit is put in fifo after the first reporting time period with sub-carrier is detected. logic 0 is used for the initially detected phase, while logic 1 indicates inverted phase comparing to the initial phase. end of receive is reported when the first reporting period without sub-carrier is detected. figure 28 shows an example for setting scf = 01b and scp = 01b. with this setting the sub- carrier frequency is set to fc/8 (1695 khz) and the reporting period to two sub-carrier periods (16/fc ~1.18 s). 0 6 9 ' d w d l q ) , ) 2 , q s x w v l j q d o i f i f docid029656 rev 2 71/129 ST25R3911B functional overview 71 figure 28. example of bpsk stream mode for scf = 01b and scp = 10b reader to tag communication in stream mode reader to tag communication control is the same for both stream modes. reader to tag coding is defined by data put in fifo. the stx bits of stream mode definition register define the tx time period during which one bit of fifo data define the status of transmitter. in case the data bit is set to logic 0 there is no modulati on, in case it is logic 1 the transmitted carrier signal is modulated according to current modulation type setting (am or ook). transmission in stream mode is started by sending direct commands transmit without crc or transmit with crc. figure 29 shows an example for setting stx = 000b. with this setting th e tx time period is defined to 128/fc (~9,44 s). figure 29. example of tx in stream mode for stx = 000b and ook modulation 0 6 9 ' d w d l q ) , ) 2 , q s x w v l j q d o i f i f 0 6 9 ' d w d l q ) , ) 2 , q s x w v l j q d o i f ST25R3911B 72/129 docid029656 rev 2 1.3 registers the 6-bit register addresses below are def ined in hexadecimal notation. the possible addresses range from 00h to 3fh. there are two types of registers implemented in the ST25R3911B: ? configuration registers ? display registers the configuration registers are used to conf igure the ST25R3911B. they can be read and written (rw) through the spi. the display registers are read only (r); they contain information about the ST25R3911B internal state. registers are set to their default state at power-up and after sending direct command set default. the exceptions are io configuration register 1 , io configuration register 2 and operation control register . these registers are related to the hardware configuration and are reset to their default state only at power-up. table 17. registers map address (hex) main function content comment type 00 io configuration io configuration register 1 set to default state only at power-up rw 01 io configuration register 2 rw 02 operation control and mode definition operation control register set to default state only at power-up rw 03 mode definition register -rw 04 bit rate definition register -rw 05 configuration iso14443a and nfc 106kb/s settings register -rw 06 iso14443b settings register 1 -rw 07 iso14443b and felica settings register -rw 08 stream mode definition register -rw 09 auxiliary definition register -rw 0a receiver configuration register 1 -rw 0b receiver configuration register 2 -rw 0c receiver configuration register 3 -rw 0d receiver configuration register 4 -rw 0e timer definition mask receive timer register -rw 0f no-response timer register 1 -rw 10 no-response timer register 2 -rw 11 general purpose and no-response timer control register -rw 12 general purpose timer register 1 -rw 13 general purpose timer register 2 -rw docid029656 rev 2 73/129 ST25R3911B 116 14 interrupt and associated reporting main interrupt register -rw 15 mask timer and nfc interrupt register -rw 16 mask error and wake-up interrupt register -rw 17 main interrupt register -r 18 mask timer and nfc interrupt register -r 19 error and wake-up interrupt register -r 1a fifo status register 1 -r 1b fifo status register 2 -r 1c collision display register -r 1d definition of transmitted bytes number of transmitted bytes register 1 -rw 1e number of transmitted bytes register 2 -rw 1f nfcip bit rate detection display nfcip bit rate detection display register -r 20 a/d converter output a/d converter output register -r 21 antenna calibration antenna calibration control register -rw 22 antenna calibration target register -rw 23 antenna calibration display register -r 24 am modulation depth and antenna driver am modulation depth control register -rw 25 am modulation depth display register -r 26 rfo am modulated level definition register -rw 27 rfo normal level definition register -rw 29 external field detector threshold external field detector threshold register -rw 2a regulator regulator voltage control register -rw 2b regulator and timer display register -r 2c receiver state display rssi display register -r 2d gain reduction state register -r 2e capacitive sensor capacitive sensor control register -rw 2f capacitive sensor display register -r 30 auxiliary display auxiliary display register -r table 17. registers map (continued) address (hex) main function content comment type ST25R3911B 74/129 docid029656 rev 2 31 wake-up wake-up timer control register -rw 32 amplitude measurement configuration register -rw 33 amplitude measurement reference register -rw 34 amplitude measurement auto-averaging display register -r 35 amplitude measurement display register -r 36 phase measurement configuration register -rw 37 phase measurement reference register -rw 38 phase measurement auto-averaging display register -r 39 phase measurement display register -r 3a capacitance measurement configuration register -rw 3b capacitance measurement reference register -rw 3c capacitance measurement auto-averaging display register -r 3d capacitance measurement display register -r 3f ic identity ic identity register -r table 17. registers map (continued) address (hex) main function content comment type docid029656 rev 2 75/129 ST25R3911B 116 1.3.1 io configur ation register 1 address: 00h type: rw table 18. io configuration register 1 (1) bit name default function comments 7 single 0 1: only one rfo driver will be used choose between single and differential antenna driving 6rfo2 0 0: rfo1, rfi1 1: rfo2, rfi2 choose which output driver and which input will be used in case of single driving 5 fifo_lr 0 0: 64 1: 80 fifo water level for receive 4 fifo_lt 0 0: 32 1: 16 fifo water level for transmit 3 osc 1 0: 13.56 mhz xtal 1: 27.12 mhz xtal selector for crystal oscillator 2 out_cl1 0 out_cl1 out_cl0 mcu_clk selection of clock frequency on mcu_clk output in case xtal oscillator is running. in case of ?11? mcu_clk output is permanently low. 003.39 mhz 016.78 mhz 1 out_cl0 0 1 0 13.56 mhz 1 1 disabled 0 lf_clk_off 0 1: no lf clock on mcu_clk by default the 32 khz lf clock is present on mcu_clk output when xtal oscillator is not running and the mcu_clk output is not disabled. 1. default setting takes place at power-up only. ST25R3911B 76/129 docid029656 rev 2 1.3.2 io configur ation register 2 address: 01h type: rw table 19. io configuration register 2 (1) bit name default function comments 7 sup3 v 0 0: 5 v supply 1: 3.3 v supply 5 v supply, range: 4.1 v to 5.5 v 3.3 v supply, range: 2.4 v to 3.6 v min. 3.0 v for vhbr 6 vspd_off 0 1: disable vsp_d regulator used for low cost applications. when this bit is set: ? at 3 v or 5 v supply vsp_d and vsp_a shall be shorted externally ? at 3.3 v applications vsp_d can alternatively be supplied from v dd in case v sp_a is not more than 300 mv lower then v dd 5 - - not used - 4 miso_pd2 0 1: pull-down on miso, when /ss is low and miso is not driven by the ST25R3911B - 3 miso_pd1 0 1: pull-down on miso when /ss is high - 2 io_18 0 1: increase miso driving level in case of 1.8 v v dd_io - 1 - - not used - 0 slow_up 0 1: slow ramp at tx on 10 s, 10% to 90%, for b 1. default setting takes place at power-up only. docid029656 rev 2 77/129 ST25R3911B 116 1.3.3 operation control register address: 02h type: rw table 20. operation control register (1) bit name default function comments 7en 0 1: enables oscillator and regulator (ready mode) - 6 rx_en 0 1: enables rx operation - 5 rx_chn 0 0: both, am and pm, channels enabled 1: one channel enabled in case only one rx channel is enabled, selection is done by the receiver configuration register 1 bit ch_sel 4rx_man 0 0: automatic channel selection 1: manual channel selection in case both rx channels are enabled, it chooses the method of channel selection, manual selection is done by the receiver configuration register 1 bit ch_sel 3 tx_en 0 1: enables tx operation this bit is automatically set by nfc field on commands and reset in nfc active communication modes after transmission is finished 2 wu 0 1: enables wake-up mode according to settings in wake-up timer control register 1- - not used - 0- - - 1. default setting takes place at power-up only. ST25R3911B 78/129 docid029656 rev 2 1.3.4 mode definition register address: 03h type: rw table 21. mode definition register (1) bit name default function comments 7targ 0 0: initiator 1: target - 6om3 0 refer to table 22 and table 23 selection of operation mode different for initiator and target modes 5om2 0 4om1 0 3om0 1 2- 0 not used - 1- 0 - 0nfc_ar 0 1: automatic start response rf collision avoidance sequence automatically starts the response rf collision avoidance if an external field off is detected 1. default setting takes place at power-up and after set default command. table 22. initiator operation modes (1) 1. if a non supported operation mode is selected the tx/rx operation is disabled. om3 om2 om1 om0 comments 0000nfcip-1 active communication 0001iso 14443a 0010iso 14443b 0011felica ? 0100nfc forum type 1 tag (topaz) 1110sub-carrier stream mode 1111 bpsk stream mode other combinations not used table 23. target operation modes (1) 1. if a non supported operation mode is selected the tx/rx operation is disabled. om3 om2 om1 om0 comments 0000 nfcip-1 active communication, bit rate detection mode 0001 nfcip-1 active communication, normal mode other combinations not used docid029656 rev 2 79/129 ST25R3911B 116 1.3.5 bit rate definition register address: 04h type: rw table 24. bit rate definition register (1)(2) bit name default function comments 7tx_rate3 0 refer to table 25 selects bit rate for tx 6tx_rate2 0 5tx_rate1 0 4tx_rate0 0 3rx_rate3 0 selects bit rate for rx in case selected protocol allows different bit rates for rx and tx 2rx_rate2 0 1rx_rate1 0 0rx_rate0 0 1. default setting takes place at power-up and after set default command. 2. automatically loaded by direct command go to normal nfc mode. table 25. bit rate coding (1) rate3 rate2 rate1 rate0 bit rate (kbit/s) comments 0000 fc/128 (~106) - 0001 fc/64 (~212) - 0010 fc/32 (~424) - 0011 fc/16 (~848) - 0100 fc/8 (~1695) vhbr tx is s upported only for iso14443b mode vhbr rx is supported only for fc/8 and fc/4 0101 fc/4 (~3390) 0110 fc/2 (~6780) other combinations - not used 1. if a non supported bit rate is selected the tx/rx operation is disabled. ST25R3911B 80/129 docid029656 rev 2 1.3.6 iso14443a and nfc 106 kb/s settings register address: 05h type: rw table 26. iso14443a and nfc 106kb/s settings register (1) bit name default function comments 7 no_tx_par (2) 0 1: no parity bit is generated during tx data stream is taken from fifo, transmit has to be done using command transmit without crc. 6 no_rx_par (2) 0 1: receive without parity and crc when set to 1 received bi t stream is put in the fifo, no parity and crc detection is done 5nfc_f0 0 1: support of nfcip-1 transport frame format add sb (f0) and len bytes during tx and skip sb (f0) byte during rx in nfc active communication mode 4 p_len3 0 refer to table 27 modulation pulse width; defined in number of 13.56 mhz clock periods. 3 p_len2 0 2 p_len1 0 1 p_len0 0 0 antcl 0 1: iso14443 anticollision frame has to be set to 1 when iso14443a bit oriented anticollision frame is sent 1. default setting takes place at power-up and after set default command. 2. no_tx_par and no_rx_par are used to send and receive custom frames like mi fare? classic frames. table 27. iso14443a modulation pulse width p_len3 p_len2 p_len1 p_len0 pulse width in number of 1/fc for different bit rates fc/128 fc/64 fc/32 fc/16 0111 42 - - - 0 1 1 0 41 20 - - 0 1 0 1 40 21 - - 0 1 0 0 39 22 13 - 0 0 1 1 38 21 12 8 0 0 1 0 37 20 11 7 0 0 0 1 36 19 10 6 0 0 0 0 35 18 9 5 1 1 1 1 34 17 8 4 1 1 1 0 33 16 7 3 1 1 0 1 32 15 6 2 1 1 0 0 31 14 5 - 1 0 1 1 30 13 - - 1 0 1 0 29 12 - - docid029656 rev 2 81/129 ST25R3911B 116 1.3.7 iso14443b sett ings register 1 address: 06h type: rw 1001 28 - - - 1000 27 - - - table 27. iso14443a modulation pulse width (continued) p_len3 p_len2 p_len1 p_len0 pulse width in number of 1/fc for different bit rates fc/128 fc/64 fc/32 fc/16 table 28. iso14443b settings register 1 (1) bit name default function comments 7 egt2 0 egt2 egt1 egt0 number of etu egt defined in number of etu 000 0 6 egt1 0 001 1 ... ... ... ... 5 egt0 0 110 6 111 6 4 sof_0 0 0: 10 etu 1: 11 etu sof, number of etu with logic 0 (10 or 11) 3 sof_1 0 0: 2 etu 1: 3 etu sof, number of etu with logic 1 (2 or 3) 2eof 0 0: 10 etu 1: 11 etu eof, number of etu with logic 0 (10 or 11) 1 half 0 0: sof, and eof defined by sof_0, sof_1, and eof bit 1: sof 10.5, 2.5, eof: 10.5 sets sof and eof settings in middle of specification 0rx_st_om 0 0: start/stop bit must be present for rx 1: start/stop bit omission for rx sof= fixed to 10 low - 2 high, eof not defined, put in fifo last full byte (2) 1. default setting takes place at power-up and after set default command. 2. start/stop bit omission for tx can be implemented by using stream mode. ST25R3911B 82/129 docid029656 rev 2 1.3.8 iso14443b and feli ca settings register address: 07h type: rw table 29. iso14443b and felica settings register (1) bit name default function comments 7tr1_1 0 refer to table 30 - 6tr1_0 0 5 no_sof 0 1: no sof picc to pcd according to iso14443-3 chapter 7.10.3.3 support of b? 4 no_eof 0 1: no eof picc to pcd according to iso14443-3 chapter 7.10.3.3 3eof_12 0 0: picc eof 10 to 11 etu 1: picc eof 10 to 12 etu support of b (2) 2 phc_th 0 1: increased tolerance of phase change detection - 1 f_p1 0 00: 48 01: 64 10: 80 11: 96 felica preamble length (valid also for nfcip-1 active communication bit rates 242 and 484 kb/s) 0f_p0 0 1. default setting takes place at power-up and after set default command. 2. detection of eof requires larger tolerance range for bit ra tes with only one sub-carrier frequency period per bit (fc/16 and higher). due to this it is not possible to distinguish between eof with 11 and 12 etu and setting this bit has no impact on eof detection. table 30. minimum tr1 codings tr1_1 tr1_0 minimum tr1 for a picc to pcd bit rate fc/128 >fc/128 0 0 80/fs 80/fs 0 1 64/fs 32/fs 1 0 not used not used 1 1 not used not used docid029656 rev 2 83/129 ST25R3911B 116 1.3.9 stream mode definition register address: 08h type: rw table 31. stream mode definition register (1) bit name default function comments 70 - - 6 scf1 0 refer to table 32 sub-carrier frequency definition for sub- carrier and bpsk stream mode 5 scf0 0 4 scp1 0 scp1 scp0 number of pulses number of sub-carrier pulses in report period for sub-carrier and bpsk stream mode 0 0 1 (bpsk only) 01 2 3 scp0 0 10 4 11 8 2stx2 0 refer to table 33 definition of time period for tx modulator control (for sub-carrier and bpsk stream mode) 1stx1 0 0stx0 1. default setting takes place at power-up and after set default command. table 32. sub-carrier frequency definition for sub-carrier and bpsk stream mode scf1 scf0 sub-carrier mode bpsk mode 0 0 fc/64 (212 khz) fc/16 (848 khz) 0 1 fc/32 (424 khz) fc/8 (1695 khz) 1 0 fc/16 (848 khz) fc/4 (3390 khz) 1 1 fc/8 (1695 khz) not used table 33. definition of time period for stream mode tx modulator control stx2 stx1 stx0 time period 0 0 0 fc/128 (106 khz) 0 0 1 fc/64 (212 khz) 0 1 0 fc/32 (424 khz) 0 1 1 fc/16 (848 khz) 1 0 0 fc/8 (1695 khz) 1 0 1 fc/4 (3390 khz) 1 1 0 fc/2 (6780 khz) 1 1 1 not used ST25R3911B 84/129 docid029656 rev 2 1.3.10 auxiliary definition register address: 09h type: rw table 34. auxiliary definition register (1) bit name default function comments 7 no_crc_rx 0 1: receive without crc valid for all protocols, for iso14443a reqa, wupa and anticollision receive without crc is done automatically (2) 6 crc_2_fifo 0 1: make crc check, but put crc bytes in fifo and add them to number of receive bytes needed for emv compliance 5tr_am 0 0: ook 1: am set automatically by command analog preset, can be modified by register write, has to be defined for transparent and bit stream mode tx 4 en_fd 0 1: enable external field detector external field detector with peer detection threshold is activated. preset for nfcip-1 active communication mode 3 ook_hr 0 1: put rfo driver in tristate during ook modulation valid for all protocols using ook modulation (also in transparent mode) 2rx_tol 1 1: bpsk fc/32: more tolerant bpsk decoder for bit rate fc/32, iso14443a fc/128, nfcip-1 fc/128: more tolerant processing of first byte - 1nfc_n1 0 - value of n for direct commands nfc initial field on and nfc response field on (0 ... 3) 0nfc_n0 0 1. default setting takes place at power-up and after set default command. 2. receive without crc is done automatically when reqa and wupa commands are sent using direct commands transmit reqa and transmit wupa, respectively, and in ca se anticollision is per formed setting bit antcl. docid029656 rev 2 85/129 ST25R3911B 116 1.3.11 receiver configuration register 1 address: 0ah type: rw table 35. receiver conf iguration register 1 (1) bit name default function comments 7 ch_sel 0 0: enable am channel 1: enable pm channel in case only one rx channel is enabled in the operation control register it defines which channel is enabled. in case both channels are enabled and manual channel selection is active, it defines which channel is used for receive framing. 6amd_sel 0 0: peak detector 1: mixer am demodulator type select, vhbr automatic preset to mixer 5lp2 0 low pass control (see ta ble 2 ) for automatic and other recommended filter settings, refer to ta ble 3 . 4lp1 0 3lp0 0 2 h200 0 first and third stage zero setting (see table 1 ) 1h80 0 0 z12k 0 1. default setting takes place at power-up and after set default command. ST25R3911B 86/129 docid029656 rev 2 1.3.12 receiver conf iguration register 2 address: 0bh type: rw table 36. receiver conf iguration register 2 (1) bit name default function comments 7 rx_lp 0 1: low power receiver operation - 6 lf_op 0 0: differential lf operation 1: lf input split (rfi1 to am channel, rfi2 to pm channel) - 5 lf_en 0 1: lf signal on receiver input - 4 agc_en 1 1: agc is enabled - 3 agc_m 1 0: agc operates on first eight sub-carrier pulses 1: agc operates during complete receive period - 2 agc_alg 0 0: algorithm with preset is used 1: algorithm with reset is used algorithm with preset is recommended for protocols with short sof (like iso14443a fc/128) 1 sqm_dyn 1 1: automatic squelch activation after end of tx squelch is started 18.88 s after end of tx, and stopped when mask receive timer expires 0 pmix_cl 0 0: rfo 1: internal signal pm demodulator mixer cl ock source, in single mode internal signal is always used 1. default setting takes place at power-up and after set default command. docid029656 rev 2 87/129 ST25R3911B 116 1.3.13 receiver conf iguration register 3 address: 0ch (1 st stage gain settings) type: rw 1.3.14 receiver conf iguration register 4 address: 0dh (2 nd and 3 rd stage gain settings) type: rw table 37. receiver conf iguration register 3 (1) bit name default function comments 7 rg1_am2 1 gain reduction/boost in first gain stage of am channel. 0: full gain 1-6: gain reduction 2.5 db per step (15 db total) 7: boost +5.5 db 6 rg1_am1 1 5 rg1_am0 0 4 rg1_pm2 1 gain reduction/boost in first gain stage of pm channel. 0: full gain 1-6: gain reduction 2.5 db per step (15 db total) 7: boost +5.5 db 3 rg1_pm1 1 2 rg1_pm0 0 1lim 0 1: clip output of 1 st and 2 nd stage signal clipped to 0.6 v, preset for nfcip-1 active communication mode 0 rg_nfc 0 1: forces gain reduction in 2 nd and 3 rd gain stage to -6 db and maximum comparator window preset for nfcip-1 active communication mode. after clearing this bit, receiver must be restarted. 1. default setting takes place at power-up and after set default command. table 38. receiver configuration register 4 (1)(2) bit name default function comments 7 rg2_am3 0 am channel: gain reduction in second and third stage and digitizer only values from 0h to ah are used: ? settings 1h to 4h reduce gain by increasing the digitizer window in 3db steps ? values from 5h to ah additionally reduce the gain in 2 nd and 3 rd gain stage, always in 3 db steps. 6 rg2_am2 0 5 rg2_am1 0 4 rg2_am0 0 3 rg2_pm3 0 pm channel: gain reduction in second and third stage and digitizer only values from 0h to ah are used: ? settings 1h to 4h reduce gain by increasing the digitizer window in 3db steps ? values from 5h to ah additionally reduce the gain in 2 nd and 3 rd gain stage, always in 3 db steps. 2 rg2_pm2 0 1 rg2_pm1 0 0 rg2_pm0 0 1. default setting takes place at power-up and after set default command. 2. sending of direct command reset rx gain is necessary to l oad the value of this register into agc, squelch, and rssi block. ST25R3911B 88/129 docid029656 rev 2 1.3.15 mask recei ve timer register address: 0eh type: rw table 39. mask receive timer register (1)(2) bit name default function comments 7 mrt7 0 defined in steps of 64/fc (4.72 s). range from 256/fc (~18.88 s) to 16320/fc (~1.2 ms) timeout = mrt<7:0> * 64/fc timeout (0 mrt<7:0> 4) = 4 * 64/fc (18.88 s) in nfcip-1 bit rate detection mode one step is 512/fc (37.78 s) defines time after end of tx during which receiver output is masked (ignored). for the case of iso14443a 106 kbit/s the mask receive timer is defined according to pcd to picc frame delay time definition, where bits mrt<7:0> define the number of n/2 steps. minimum mask receive time of 18.88 s covers the transients in receiver after end of transmission. 6 mrt6 0 5 mrt5 0 4 mrt4 0 3 mrt3 1 2 mrt2 0 1 mrt1 0 0 mrt0 0 1. default setting takes place at power-up and after set default command. 2. in nfcip-1 bit rate detection mode, the clock of the mask re ceive timer is additionally divid ed by eight (one count is 512/fc ) to cover range up to ~9.6 ms. docid029656 rev 2 89/129 ST25R3911B 116 1.3.16 no-response timer register 1 address: 0fh type: rw 1.3.17 no-response timer register 2 address: 10h type: rw table 40. no-response timer register 1 (1) bit name default function comments 7nrt15 0 no-response timer definition msb bits defined in steps of 64/fc (4.72 s). range from 0 to 309 ms if bit nrt_step in general purpose and no-response timer control register is set the step is changed to 4096/fc defines timeout after end of tx. in case this timeout expires without detecting a response a no-response interrupt is sent. in nfc mode the no-response timer is started only when external field is detected. in the nfcip-1 active communication mode the no-response timer is autom atically started when the transmitter is turned off after the message has been sent all 0: no-response timer is not started. no-response timer is reset and restarted with start no-response timer direct command. 6nrt14 0 5nrt13 0 4nrt12 0 3nrt11 0 2nrt10 0 1nrt9 0 0nrt8 0 1. default setting takes place at power-up and after set default command. table 41. no-response timer register 2 (1) bit name default function comments 7nrt7 0 no-response timer definition lsb bits - 6nrt6 0 5nrt5 0 4nrt4 0 3nrt3 0 2nrt2 0 1nrt1 0 0nrt0 0 1. default setting takes place at power-up and after set default command. ST25R3911B 90/129 docid029656 rev 2 1.3.18 general purpose and no -response timer control register address: 11h type: rw table 42. general purpose and no-response timer control register (1) bit name default function comments 7gptc2 0 defines the timer trigger source. refer to table 43 . - 6gptc1 0 - 5gptc0 0 - 4- 0 - - 3- 0 - - 2- 0 - - 1 nrt_emv 0 1: emv mode of no-response timer - 0nrt_step 0 0: 64/fc 1: 4096/fc selects the no-response timer step. 1. default setting takes place at power-up and after set default command. table 43. timer trigger source gptc2 gptc1 gptc0 trigger source 000 no trigger source, start only with direct command start general purpose timer. 0 0 1 end of rx (after eof) 010start of rx 011 end of tx in nfc mode, when general purpose timer expires the field is switched off 100 not used 101 110 111 docid029656 rev 2 91/129 ST25R3911B 116 1.3.19 general purpose timer register 1 address: 12h type: rw 1.3.20 general purpose timer register 2 address: 13h type: rw table 44. general purpose timer register 1 (1) bit name default function comments 7 gpt15 - general purpose timeout definition msb bits defined in steps of 8/fc (590 ns) range from 590 ns to 38,7 ms - 6 gpt14 - 5 gpt13 - 4 gpt12 - 3gpt11 - 2 gpt10 - 1gpt9 - 0gpt8 - 1. default setting takes place at power-up and after set default command. table 45. general purpose timer register 2 (1) bit name default function comments 7gpt7 - general purpose timeout definition lsb bits defined in steps of 8/fc (590 ns) range from 590 ns to 38,7 ms - 6gpt6 - 5gpt5 - 4gpt4 - 3gpt3 - 2gpt2 - 1gpt1 - 0gpt0 - 1. default setting takes place at power-up and after set default command. ST25R3911B 92/129 docid029656 rev 2 1.3.21 mask main interrupt register address: 14h type: rw 1.3.22 mask timer and nfc interrupt register address: 15h type: rw table 46. mask main interrupt register (1) bit name default function comments 7 m_osc 0 1: mask irq when oscillator frequency is stable - 6 m_wl 0 1: mask irq due to fifo water level - 5 m_rxs 0 1: mask irq due to start of receive - 4 m_rxe 0 1: mask irq due to end of receive - 3 m_txe 0 1: mask irq due to end of transmission - 2 m_col 0 1: mask irq due to bit collision - 1- 0 not used - 0- 0 - 1. default setting takes place at power-up and after set default command. table 47. mask timer and nfc interrupt register (1) bit name default function comments 7 m_dct 0 1: mask irq due to termination of direct command - 6 m_nre 0 1: mask irq due to no-response timer expire - 5 m_gpe 0 1: mask irq due to general purpose timer expire - 4 m_eon 0 1: mask irq due to detection of external field higher than target activation level - 3 m_eof 0 1: mask irq due to detection of external field drop below target activation level - 2m_cac 0 1: mask irq due to detection of collision during rf collision avoidance - 1 m_cat 0 1: mask irq after minimum guard time expire - 0m_nfct 0 1: mask irq when in target mode the initiator bit rate was recognized - 1. default setting takes place at power-up and after set default command. docid029656 rev 2 93/129 ST25R3911B 116 1.3.23 mask error and w ake-up interrupt register address: 16h type: rw 1.3.24 main interrupt register address: 17h type: r table 48. mask error and wake-up interrupt register (1) bit name default function comments 7 m_crc 0 1: mask irq due to crc error - 6 m_par 0 1: mask irq due to parity error - 5 m_err2 0 1: mask irq due to soft framing error - 4 m_err1 0 1: mask irq due to hard framing error - 3 m_wt 0 1: mask irq due to wake-up timer interrupt - 2 m_wam 0 1: mask wake-up irq due to amplitude measurement - 1 m_wph 0 1: mask wake-up irq due to phase measurement. - 0 m_wcap 0 1: mask wake-up irq due to capacitance measurement - 1. default setting takes place at power-up and after set default command. table 49. main interrupt register (1)(2) bit name default function comments 7 i_osc - irq when oscillator frequency is stable set after oscillator is started by setting operation control register bit en. 6 i_wl - irq due to fifo water level set during receive, informing that fifo is almost full and has to be read out. set during transmit, informing that fifo is almost empty and that additional data has to be sent. 5 i_rxs - irq due to start of receive - 4 i_rxe - irq due to end of receive - 3 i_txe - irq due to end of transmission - 2 i_col - irq due to bit collision - 1 i_tim - irq due to timer or nfc event details in timer and nfc interrupt register 0 i_err - irq due to error and wake-up timer details in error and wake-up interrupt register 1. at power-up and after set default command content of this register is set to 0. 2. after main interrupt register has been read, its content is set to 0, except for bits 1 and 0, which are set to 0 after corresponding interrupt register is read. ST25R3911B 94/129 docid029656 rev 2 1.3.25 timer and nfc interrupt register address: 18h type: r table 50. timer and nfc interrupt register (1)(2) bit name default function comments 7 i_dct - irq due to termination of direct command - 6i_nre - irq due to no-response timer expire - 5 i_gpe - irq due to general purpose timer expire - 4 i_eon - irq due to detection of external field higher than target activation level - 3 i_eof - irq due to detection of external field drop below target activation level - 2 i_cac - irq due to detection of collision during rf collision avoidance an external field was detected during rf collision avoidance 1i_cat - irq after minimum guard time expire an external field was not detected during rf collision avoidance, field was switched on, irq is sent after minimum guard time according to nfcip-1 0 i_nfct - irq when in target mode the initiator bit rate was recognized - 1. at power-up and after set default command content of this register is set to 0. 2. after main interrupt register has been read, its content is set to 0. docid029656 rev 2 95/129 ST25R3911B 116 1.3.26 error and wake-up interrupt register address: 19h type: r table 51. error and wake-up interrupt register (1)(2) bit name default function comments 7 i_crc - crc error - 6 i_par - parity error - 5 i_err2 - soft framing error framing error which does not result in corrupted rx data 4 i_err1 - hard framing error framing erro r which results in corrupted rx data 3 i_wt - wake-up timer interrupt timeout after execution of start wake-up timer command in case option with irq at every timeout is selected 2 i_wam - wake-up interrupt due to amplitude measurement result of amplitude measurement was ? am larger than reference 1i_wph - wake-up interrupt due to phase measurement. result of phase measurement was ? pm larger than reference 0i_wcap - wake-up interrupt due to capacitance measurement result of capacitance measurement was ? cm larger than reference 1. at power-up and after set default command content of this register is set to 0. 2. after main interrupt register has been read, its content is set to 0. ST25R3911B 96/129 docid029656 rev 2 1.3.27 fifo stat us register 1 address: 1ah type: r 1.3.28 fifo stat us register 2 address: 1bh type: r table 52. fifo status register 1 (1) bit name default function comments 7- - - - 6 fifo_b6 - number of bytes (binary coded) in the fifo which were not read out valid range is from 0 (000 0000b) to 96 (110 0000b) 5 fifo_b5 - 4 fifo_b4 - 3 fifo_b3 - 2 fifo_b2 - 1 fifo_b1 - 0 fifo_b0 - 1. at power-up and after set default command content of this register is set to 0. table 53. fifo status register 2 (1)(2) bit name default function comments 7- - - - 6 fifo_unf - 1: fifo underflow set when more bytes then actual content of fifo were read 5 fifo_ovr - 1: fifo overflow - 4 fifo_ncp - 1: last fifo byte is not complete - 3fifo_lb2 - number of bits in the last fifo byte if it was not complete (fifo_ncp=1) in case of incomplete by te the lsb part is valid 2fifo_lb1 - 1fifo_lb0 - 0np_lb - 1: parity bit is missing in last byte this is a framing error 1. at power-up and after set default command content of this register is set to 0. 2. if fifo is empty, the value of register fifo status register 1 (0x1ah) is 0x00, register bits fifo_ncp, fifo_lb2, fifo_lb1 and fifo_lb0 in register block 0x1bh are cleared. co rrect procedure for fifo read is to read both fifo status register 1 and fifo status register 2 and then read fifo. second register values need to be saved in mcu, if non-complete bytes are in fifo. docid029656 rev 2 97/129 ST25R3911B 116 1.3.29 collision display register address: 1ch type: r 1.3.30 number of transm itted bytes register 1 address: 1dh type: rw table 54. collision display register (1) bit name default function comments 7 c_byte3 - number of full bytes before the bit collision happened. the collision display register range covers iso14443a anticollision command. in case collision (or framing error that is interpreted as collision) happens in a longer message, the collision display register is not set. 6 c_byte2 - 5 c_byte1 - 4 c_byte0 - 3c_bit2 - number of bits before the collision in the byte where the collision happened 2c_bit1 - 1c_bit0 - 0 c_pb - 1: collision in parity bit this is an error, reported in case it is the first collision detected 1. at power-up and after set default command content of this register is set to 0. table 55. number of transmitted bytes register 1 (1) bit name default function comments 7ntx12 0 number of full bytes to be transmitted in one command, msb bits maximum supported number of bytes is 8191 6ntx11 0 5ntx10 0 4ntx9 0 3ntx8 0 2ntx7 0 1ntx6 0 0ntx5 0 1. default setting takes place at power-up and after set default command. ST25R3911B 98/129 docid029656 rev 2 1.3.31 number of transm itted bytes register 2 address: 1eh type: rw 1.3.32 nfcip bit rate de tection display register address: 1fh type: r table 56. number of transmitted bytes register 2 (1)(2) bit name default function comments 7ntx4 0 number of full bytes to be transmitted in one command, msb bits maximum supported number of bytes is 8191 6ntx3 0 5ntx2 0 4ntx1 0 3ntx0 0 2 nbtx2 0 number of bits in the split byte 000 means that there is no split byte (all bytes all complete) applicable for iso14443a: bit oriented anticollision frame in case last byte is split byte tx is done without parity bit generation 1 nbtx1 0 0 nbtx0 0 1. default setting takes place at power-up and after set default command. 2. if anctl bit is set while card is in idle state and nbtx is not 000, then i_par will be triggered during wupa direct command is issued. table 57. nfcip bit rate detection display register (1) bit name default function comments 7 nfc_rate3 - refer to table 25 this register stores resu lt of automatic bit rate detection in the nfcip-1 active communication bit rate detection mode 6 nfc_rate2 - 5 nfc_rate1 - 4 nfc_rate0 - 3- - not used - 2- - 1- - 0- - 1. at power-up and after set default command content of this register is set to 0. docid029656 rev 2 99/129 ST25R3911B 116 1.3.33 a/d converter output register address: 20h type: r 1.3.34 antenna calibra tion control register address: 21h type: rw table 58. a/d converter output register (1) bit name default function comments 7ad7 - displays result of last a/d conversion. - 6ad6 - 5ad5 - 4ad4 - 3ad3 - 2ad2 - 1ad1 - 0ad0 - 1. at power-up and after set default command, see table 9 , content of this register is set to 0. table 59. antenna calibration control register (1) bit name default function comments 7 trim_s 0 0: lc trim switches are defined by result of calibrate antenna command, see table 9 1: lc trim switches are defined by bits tre_x written in this register defines source of driving switches on trimx pins 6tre_3 0msb lc trim switches are defined by data written in this register in case trim _s=1. a bit set to 1 switch on transistor on trim1_x and trim2_x pin. 5tre_2 0 - 4tre_1 0 - 3tre_0 0lsb 2- 0 -- 1- 0 0- 0 1. default setting takes place at power-up and after set default command. ST25R3911B 100/129 docid029656 rev 2 1.3.35 antenna calibration target register address: 22h type: rw 1.3.36 antenna calibra tion display register address: 23h type: r table 60. antenna calibration target register (1) bit name default function comments 7act7 1 define target phase for calibrate antenna direct command, see table 9 - 6 act6 0 - 5 act5 0 - 4 act4 0 - 3 act3 0 - 2 act2 0 - 1 act1 0 - 0 act0 0 - 1. default setting takes place at power-up and after set default command. table 61. antenna calibration display register (1) bit name default function comments 7tri_3 -msb this register stores result of calibrate antenna command. lc trim switches are defined by data written in this register in case trim_s = 0. a bit set to 1 indicates that corresponding transistor on trim1_x and trim2_x pin is switched on. 6tri_2 - - 5tri_1 - - 4tri_0 -lsb 3 tri_err - 1: antenna calibration error set when calibrate antenna sequence has not been able to adjust resonance 2- - not used - 1- - 0- - 1. at power-up and after set default command content of this register is set to 0. docid029656 rev 2 101/129 ST25R3911B 116 1.3.37 am modulation depth control register address: 24h type: rw 1.3.38 am modulation depth display register address: 25h type: r table 62. am modulation depth control register (1) bit name default function comments 7am_s 0 0: am modulated level is defined by bits mod5 to mod0. level is adjusted automatically by calibrate modulation depth command, see table 9 1: am modulated level is defined by bits dram7 to dram0. - 6 mod5 0 msb see section 1.2.20: am modulation depth: definition and calibration on page 63 for details about am modulation lavel definition. 5 mod4 0 - 4 mod3 0 - 3 mod2 0 - 2 mod1 0 - 1 mod0 0 lsb 0- 0 - - 1. default setting takes place at power-up and after set default command. table 63. am modulation depth display register (1) bit name default function comments 7md_7 -msb displays result of calibrate modulation depth command. antenna drivers are composed of 8 binary weighted segments. bit md_x set to one indicates that this particular segment will be disabled during am modulated state. in case of error all 1 value is set. 6md_6 - - 5md_5 - - 4md_4 - - 3md_3 - - 2md_2 - - 1md_1 - - 0 md_0 - lsb 1. at power-up and after set default command content of this register is set to 0. ST25R3911B 102/129 docid029656 rev 2 1.3.39 rfo am modulated level definition register address: 26h type: rw 1.3.40 rfo normal l evel definition register address: 27h type: rw applying value ffh to t he register 27h will put th e drivers in tristate. table 64. rfo am modulated level definition register (1) bit name default function comments 7 dram7 0 2 ohm antenna drivers are composed of eight binary weighted segments. setting a bit dram to 1 will disable corresponding segment during am modulated state in case am_s bit is set to 1. 6 dram6 0 4 ohm 5 dram5 0 8 ohm 4 dram4 0 16 ohm 3 dram3 0 32 ohm 2 dram2 0 64 ohm 1 dram1 0 128 ohm 0 dram0 0 256 ohm 1. default setting takes place at power-up and after set default command. table 65. rfo normal level definition register (1) bit name default function comments 7droff7 02 ohm antenna drivers are composed of eight binary weighted segments. setting a bit droff to 1 will disable corresponding segment during normal non-modulated operation. the tx drivers are made up of 8 segments, binary weighted from 2 to 256 ohm (nominal). as an example, setting this register to 0xc0 disables the 2 ohm and 4 ohm segments. 6droff6 04 ohm 5droff5 08 ohm 4droff4 016 ohm 3droff3 032 ohm 2droff2 064 ohm 1 droff1 0 128 ohm 0 droff0 0 256 ohm 1. default setting takes place at power-up and after set default command. docid029656 rev 2 103/129 ST25R3911B 116 1.3.41 external field de tector threshold register address: 29h type: rw 75 105 150 205 290 400 560 800 table 66. external field detector threshold register (1) bit name default function comments 7 - 0 not used - 6trg_l2 0 peer detection threshold. refer to table 67 . - 5trg_l1 1 4trg_l0 1 3rfe_t3 0 collision avoidance threshold. refer to table 68 . - 2rfe_t2 0 1rfe_t1 1 0rfe_t0 1 1. default setting takes place at power-up and after set default command. table 67. peer detection threshold as seen on rfi1 input trg_i2 trg_i1 trg_i0 target peer detection threshold voltage (mv pp on rfi1) 000 001 010 011 100 101 110 111 table 68. collision avoidance threshold as seen on rfi1 input rfe_3 rfe_2 rfe_1 rfe_0 typical collision avoidance threshold voltage (mv pp on rfi1) 0000 75 0001 105 0010 150 0011 205 0100 290 0101 400 0110 560 ST25R3911B 104/129 docid029656 rev 2 1.3.42 regulator volt age control register address: 2ah type: rw 0111 800 1000 25 1001 33 1010 47 1011 64 1100 90 1101 125 1110 175 1111 250 table 68. collision avoidance threshold as seen on rfi1 input (continued) rfe_3 rfe_2 rfe_1 rfe_0 typical collision avoidance threshold voltage (mv pp on rfi1) table 69. regulator voltage control register (1) bit name default function comments 7 reg_s 0 0: regulated voltages are defined by result of adjust regulators command 1: regulated voltages are defined by rege_x bits written in this register defines mode of regulator voltage setting. 6 rege_3 0 external definition of regulated voltage. refer to table 71 for definition. in 5 v mode v sp_d and v sp_a regulators are set to 3.4 v - 5 rege _2 0 4 rege _1 0 3 rege _0 0 2 mpsv1 0 00: v dd 01: v sp_a 10: v sp_d 11: v sp_rf defines source of direct command measure power supply. 1 mpsv0 0 0- 0 - - 1. default setting takes place at power-up and after set default command. docid029656 rev 2 105/129 ST25R3911B 116 1.3.43 regulator and timer display register address: 2bh type: r table 70. regulator and timer display register (1) bit name default function comments 7 reg_3 - actual regulated voltage setting. refer to table 71 for definition. - 6 reg_2 - 5 reg_1 - 4 reg_0 - 3- - - - 2 gpt_on - 1: general purpose timer is running 1 nrt_on - 1: no-response timer is running 0 mrt_on - 1: mask receive timer is running 1. 1. at power-up and after set default command regulated voltage is set to maximum 3.4v. table 71. regulated voltages reg_3 reg_2 reg_1 reg_0 typical regulated voltage (v) rege_3 rege_2 rege_1 rege_0 5 v mode 3.3 v mode 11115.13.4 1 1 1 0 4.98 3.3 1 1 0 1 4.86 3.2 1 1 0 0 4.74 3.1 1 0 1 1 4.62 3.0 1 0 1 0 4.50 2.9 1 0 0 1 4.38 2.8 1 0 0 0 4.26 2.7 0 1 1 1 4.14 2.6 0 1 1 0 4.02 2.5 0 1 0 1 3.90 2.4 other combinations not used ST25R3911B 106/129 docid029656 rev 2 1.3.44 rssi display register address: 2ch type: r table 72. rssi display register (1)(2) bit name default function comments 7 rssi_am_3 - am channel rssi peak value. refer to table 73 for definition. stores peak value of am channel rssi measurement. automatically cleared at beginning of transponder message and with clear rssi command. 6 rssi_am_2 - 5 rssi_am_1 - 4 rssi_am_0 - 3 rssi_pm_3 - pm channel rssi peak value. refer to table 73 for definition. stores peak value of pm channel rssi measurement. automatically cleared at beginning of transponder message and with clear rssi command. 2 rssi_pm_2 - 1 rssi_pm_1 - 0 rssi_pm_0 - 1. at power-up and after set default command content of this register is set to 0. 2. bit 0x30[7] indicates which rssi value is use in the logic for internal use. table 73. rssi rssi_3 rssi_2 rssi_1 rssi_0 typical signal on rfi1 (mv rms ) 0000 20 0001 >20 0010 >27 0011 >37 0100 >52 0101 >72 0110 >99 0111 >136 1000 >190 1001 >262 1010 >357 1011 >500 1100 >686 1101 >950 1110 not used 1111 docid029656 rev 2 107/129 ST25R3911B 116 1.3.45 gain reduction state register address: 2dh type: r 1.3.46 capacitive sens or control register address: 2eh type: rw 7 cs_mcal4 0 manual calibration value. all 0 value enables automatic cali bration mode binary weighted, step 0.1 pf, max 3.1 pf 6 cs_mcal3 0 5 cs_mcal2 0 4 cs_mcal1 0 3 cs_mcal0 0 2 cs_g2 0 000: 2.8 v/pf 001: 6.5 v/pf 010: 1.1 v/pf 100: 0.5 v/pf 110: 0.35 v/pf others: not used capacitor sensor gain typical values 1 cs_g1 0 0 cs_g0 0 table 74. gain reduction state register (1) bit name default function comments 7 gs_am_3 - msb actual gain reduction of second stage of am channel (including register gain reduction, squelch and agc) 6 gs_am_2 - - 5 gs_am_1 - - 4 gs_am_0 - lsb 3 gs_pm_3 - msb actual gain reduction of second stage of pm channel (including register gain reduction, squelch and agc) 2 gs_pm_2 - - 1 gs_pm_1 - - 0 gs_pm_0 - lsb 1. at power-up and after set default command content of this register is set to 0. table 75. capacitive sensor control register (1) bit name default function comments 1. at power-up and after set default command content of this register is set to 0. ST25R3911B 108/129 docid029656 rev 2 1.3.47 capacitive sens or display register address: 2fh type: r 1.3.48 auxiliary display register address: 30h type: r table 76. capacitive sensor display register (1) bit name default function comments 7 cs_cal4 - capacitive sensor calibration value binary weighted, step 0.1 pf, max 3.1 pf 6 cs_cal3 - 5 cs_cal2 - 4 cs_cal1 - 3 cs_cal0 - 2 cs_cal_end - 1: calibration ended - 1 cs_cal_err - 1: calibration error - 0- - - - 1. at power-up and after set default command content of this register is set to 0. table 77. auxiliary display register (1) bit name default function comments 7a_cha - 0: am 1: pm currently selected channel 6 efd_o - 1: external field detected external field detector output 5 tx_on - 1: transmission is active - 4 osc_ok - 1: xtal osci llation is stable indication that xtal oscillator is active and its output is stable 3 rx_on - 1: receive coder is enabled - 2 rx_act - 1: receive coder is receiving a message - 1nfc_t - 1: external field detector is active in peer detection mode - 0 en_ac - 1: external field detector is active in rf collision avoidance mode - 1. at power-up and after set default command content of this register is set to 0. docid029656 rev 2 109/129 ST25R3911B 116 1.3.49 wake-up time r control register address: 31h type: rw table 78. wake-up timer control register (1) bit name default function comments 7wur 0 0: 100 ms 1: 10 ms wake-up timer range 6wut2 0 refer to table 79 wake-up timer timeout value 5wut1 0 4wut0 0 3 wto 0 1: irq at every timeout - 2wam 0 1: at timeout perform amplitude measurement irq if difference larger than ? am 1wph 0 1: at timeout perform phase measurement irq if difference larger than ? pm 0wcap 0 1: at timeout perform capacitance measurement irq if difference larger than ? cm 1. default setting takes place at power-up and after set default command. table 79. typical wake-up time wut2 wut1 wut0 100 ms range (wur=0) 10 ms range (wur=1) 0 0 0 100 ms 10 ms 0 0 1 200 ms 20 ms 0 1 0 300 ms 30 ms 0 1 1 400 ms 40 ms 1 0 0 500 ms 50 ms 1 0 1 600 ms 60 ms 1 1 0 700 ms 70 ms 1 1 1 800 ms 80 ms ST25R3911B 110/129 docid029656 rev 2 1.3.50 amplitude measurem ent configurat ion register address: 32h type: rw 1.3.51 amplitude measur ement reference register address: 33h type: rw table 80. amplitude measurem ent configuration register (1) bit name default function comments 7 am_d3 0 definition of ? am (difference to reference that triggers interrupt) - 6 am_d2 0 5 am_d1 0 4 am_d0 0 3am_aam 0 0: exclude the irq measurement 1: include the irq measurement include/exclude the measurement that causes irq (having difference > ? am to reference) in auto-averaging 2 am_aew1 0 00: 4 01: 8 10: 16 11: 32 define weight of last measurement result for auto-averaging 1 am_aew2 0 0 am_ae 0 0: use amplitude measurement reference register 1: use amplitude measurement auto-averaging as reference select reference value for amplitude measurement wake-up mode 1. default setting takes place at power-up and after set default command. table 81. amplitude measurement reference register (1) bit name default function comments 7 am_ref7 0 - - 6 am_ref6 0 - - 5 am_ref5 0 - - 4 am_ref4 0 - - 3 am_ref3 0 - - 2 am_ref2 0 - - 1 am_ref1 0 - - 0 am_ref0 0 - - 1. default setting takes place at power-up and after set default command. docid029656 rev 2 111/129 ST25R3911B 116 1.3.52 amplitude measurement au to-averaging display register address: 34h type: r 1.3.53 amplitude measur ement display register address: 35h type: r table 82. amplitude measurement auto-averaging display register (1) bit name default function comments 7 amd_aad7 0 - - 6 amd_aad6 0 - - 5 amd_aad5 0 - - 4 amd_aad4 0 - - 3 amd_aad3 0 - - 2 amd_aad2 0 - - 1 amd_aad1 0 - - 0 amd_aad0 0 - - 1. at power-up and after set default command content of this register is set to 0. table 83. amplitude measurement display register (1) bit name default function comments 7am_amd7 0 - - 6am_amd6 0 - - 5am_amd5 0 - - 4am_amd4 0 - - 3am_amd3 0 - - 2am_amd2 0 - - 1am_amd1 0 - - 0am_amd0 0 - - 1. at power-up and after set default command content of this register is set to 0. ST25R3911B 112/129 docid029656 rev 2 1.3.54 phase measurement configuration register address: 36h type: rw 1.3.55 phase measureme nt reference register address: 37h type: rw table 84. phase measurement configuration register (1) bit name default function comments 7pm_d3 0 definition of ? pm (difference to reference that triggers interrupt) - 6pm_d2 0 5pm_d1 0 4pm_d0 0 3 pm_aam 0 0: exclude the irq measurement 1: include the irq measurement include/exclude the meas urement that causes irq (having difference > ? pm to reference) in auto-averaging 2 pm_aew1 0 00: 4 01: 8 10: 16 11: 32 define weight of last measurement result for auto-averaging 1 pm_aew0 0 0pm_ae 0 0: use phase measurement reference register 1: use phase measurement auto-averaging as reference select reference value for phase measurement wake-up mode 1. default setting takes place at power-up and after set default command. table 85. phase measurement reference register (1) bit name default function comments 7pm_ref7 0 - - 6pm_ref6 0 - - 5pm_ref5 0 - - 4pm_ref4 0 - - 3pm_ref3 0 - - 2pm_ref2 0 - - 1pm_ref1 0 - - 0pm_ref0 0 - - 1. default setting takes place at power-up and after set default command. docid029656 rev 2 113/129 ST25R3911B 116 1.3.56 phase measurement au to-averaging display register address: 38h type: r 1.3.57 phase measureme nt display register address: 39h type: r table 86. phase measurement auto-averaging display register (1) bit name default function comments 7 pm_aad7 0 - - 6 pm_aad6 0 - - 5 pm_aad5 0 - - 4 pm_aad4 0 - - 3 pm_aad3 0 - - 2 pm_aad2 0 - - 1 pm_aad1 0 - - 0 pm_aad0 0 - - 1. at power-up and after set default command content of this register is set to 0. table 87. phase measurement display register (1) bit name default function comments 7pm_amd7 0 0 - 6pm_amd6 0 0 - 5pm_amd5 0 0 - 4pm_amd4 0 0 - 3pm_amd3 0 0 - 2pm_amd2 0 0 - 1pm_amd1 0 0 - 0pm_amd0 0 0 - 1. at power-up and after set default command content of this register is set to 0. ST25R3911B 114/129 docid029656 rev 2 1.3.58 capacitance measurem ent configuration register address: 3ah type: rw 1.3.59 capacitance measurement reference register address: 3bh type: rw table 88. capacitance measurement configuration register (1) bit name default function comments 7cm_d3 0 definition of ? cm (difference to reference that triggers interrupt) - 6cm_d2 0 5cm_d1 0 4cm_d0 0 3 cm_aam 0 0: exclude the irq measurement 1: include the irq measurement include/exclude the measurement that causes irq (having difference > ? cm to reference) in auto-averaging 2 cm_aew1 0 00: 4 01: 8 10: 16 11: 32 define weight of last measurement result for auto-averaging 1 cm_aew0 0 0cm_ae 0 0: use capacitance measurement reference register 1: use capacitance measurement auto-averaging as reference select reference value for capacitance measurement wake-up mode 1. default setting takes place at power-up and after set default command. table 89. capacitance measurement reference register (1) bit name default function comments 7 cm_ref7 0 - - 6 cm_ref6 0 - - 5 cm_ref5 0 - - 4 cm_ref4 0 - - 3 cm_ref3 0 - - 2 cm_ref2 0 - - 1 cm_ref1 0 - - 0 cm_ref0 0 - - 1. default setting takes place at power-up and after set default command. docid029656 rev 2 115/129 ST25R3911B 116 1.3.60 capacitance measurement auto-averaging display register address: 3ch type: r 1.3.61 capacitance meas urement display register address: 3dh type: r table 90. capacitance measurement auto-averaging display register (1) bit name default function comments 7 cm_aad7 0 - - 6 cm_aad6 0 - - 5 cm_aad5 0 - - 4 cm_aad4 0 - - 3 cm_aad3 0 - - 2 cm_aad2 0 - - 1 cm_aad1 0 - - 0 cm_aad0 0 - - 1. at power-up and after set default command content of this register is set to 0. table 91. capacitance measurement display register (1) bit name default function comments 7 cm_amd7 0 - - 6 cm_amd6 0 - - 5 cm_amd_ 0 - - 4 cm_amd_ 0 - - 3 cm_amd3 0 - - 2 cm_amd2 0 - - 1 cm_amd1 0 - - 0 cm_amd0 0 - - 1. at power-up and after set default command content of this register is set to 0. ST25R3911B 116/129 docid029656 rev 2 1.3.62 ic identity register address: 3dh type: r table 92. ic identity register bit name default function comments 7ic_type4 - code for ST25R3911B: 00001 5-bit ic type code 6ic_type3 - 5ic_type2 - 4ic_type1 - 3ic_type0 - 2 ic_rev2 - 010: silicon r3.1 011: silicon r3.3 100: silicon r4.0 3-bit ic revision code 1 ic_rev1 - 0 ic_rev0 - docid029656 rev 2 117/129 ST25R3911B pinouts and pin description 118 2 pinouts and pin description the ST25R3911B pin and pad assignments are described in figure 30 . figure 30. ST25R3911B qfn32 pinout (1) 1. the above figure shows the package top view. 0 6 9 9 ' ' b , 2 9 6 3 b ' & 6 2 ; 7 2 ; 7 , 9 6 1 b ' 9 6 3 b $ 9 ' ' 9 6 3 b 5 ) 5 ) 2 5 ) 2 9 6 1 b 5 ) 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b $ * ' 5 ) , 5 ) , 9 6 6 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 6 6 6 & / . 0 2 6 , 0 , 6 2 0 & 8 b & / . , 5 4 9 6 1 b $ & 6 , 4 ) 1 table 93. ST25R3911B pin definitions - qfn32 package pin number pin name pin type description 1 vdd_io supply pad positive supply for peripheral communication 2cso analog output capacitor sensor output 3 vsp_d digital supply regulator output 4 xto xtal oscillator output 5 xti analog input / digital input xtal oscillator input 6 vsn_d supply pad digital ground 7 vsp_a analog output analog supply regulator output 8 vdd supply pad external positive supply 9 vsp_rf analog output supply regulator output for antenna drivers 10 rfo1 antenna driver output 11 rfo2 12 vsn_rf supply pad ground of antenna drivers pinouts and pin description ST25R3911B 118/129 docid029656 rev 2 13 trim1_3 analog i/o input to trim antenna resonant circuit 14 trim2_3 15 trim1_2 16 trim2_2 17 trim1_1 18 trim2_1 19 trim1_0 20 trim2_0 21 vss supply pad ground, die substrate potential 22 rfi1 analog input receiver input 23 rfi2 24 agd analog i/o analog reference voltage 25 csi analog input capacitor sensor input 26 vsn_a supply pad analog ground 27 irq digital output interrupt request output 28 mcu_clk microcontroller clock output 29 miso digital output / tristate serial peripheral interface data output 30 mosi digital input serial peripheral interface data input 31 sclk serial peripheral interface clock 32 /ss serial peripheral interface enable (active low) 33 vss supply ground, die substrate potential, connected to v ss on pcb table 93. ST25R3911B pin definiti ons - qfn32 package (continued) pin number pin name pin type description docid029656 rev 2 119/129 ST25R3911B electrical characteristics 123 3 electrical characteristics 3.1 absolute maximum ratings stresses beyond those listed table 94 , table 95 and table 96 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in section 3.2: operating conditions is not guaranteed. exposure to absolute maximum rating conditions for extended periods may af fect device reliability. table 94. electrical parameters symbol parameter min max unit comments v dd dc supply voltage -0.5 6.0 v - v dd_io dc_io supply voltage -0.5 6.0 v - v intrim input pin voltage trim pins -0.5 25.0 v - v in input pin voltage for peripheral communication pins -0.5 6.5 v - v ina input pin voltage for analog pins -0.5 6.0 v - i scr input current (latch-up immunity) -100 100 ma norm: jedec 78 i outmax drive capability of output driver 0 600 ma - table 95. electrostatic discharge symbol parameter min max unit comments esd electrostatic discharge 2 kv standard js-001-2014 (human body model) 500 v standard js-001-2014 (human body model) valid for trimx_x pins (pins 13 - 20) table 96. temperature ranges and storage conditions symbol parameter min max unit comments t strg storage temperature -55 125 c - t body package body temperature - 260 c the refllow peak soldering temperature (body temperature) is specified according to ipc/jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic so lid state surface mount devices.? the lead finish for pb-free leaded packages is matte tin (100% sn). rh nc relative humidity non-condensing 585% - msl moisture sensitivity level 3 - represents a max. floor life time of 168 h electrical characteristics ST25R3911B 120/129 docid029656 rev 2 3.2 operating conditions all limits are guaranteed. the parameters wit h min and max values are guaranteed with production tests or sqc (statistical quality control) methods. all defined tolerances for external components in this specification need to be assured over the whole operating conditions range and over lifetime. 3.3 dc/ac characteristics for digital inputs and outputs 3.3.1 cmos inputs valid for input pins \ss, mosi, and sclk. 3.3.2 cmos outputs valid for output pins miso, irq and mcu_clk, io_18=0 ( io configuration register 2 ). table 97. operating conditions symbol parameter min max unit comments v dd positive supply voltage 2.4 5.5 v in case power supply is lower than 2.6 v, pssr cannot be improved using internal regulators (minimum regulated voltage is 2.4 v). v dd_io peripheral communication supply voltage 1.65 5.5 v v ss negative supply voltage 0 0 v - v intrim input pin voltage trim pins -20v - t jun junction temperature -40 125 c - v rfi_a rfi input amplitude 0.150 3 v pp minimum rfi input signal definition is meant for nfc receive mode. in hf reader mode and nfc transmit mode the recommended signal level is 2.5 v pp . rfo driver current 0 500 ma - table 98. cmos inputs symbol parameter min max unit v ih high level input voltage 0.7 * v dd_io v dd_io v v il low level input voltage v ss 0.3 * v dd_io v i leak input leakage current -1 1 a table 99. cmos outputs symbol parameter conditions min typ max unit v oh high level output voltage i source/sink = 1ma, measured at v ddio = 2.4 v i source/sink = 0.5 ma, measured at v ddio = 1.65 v 0.9 * v dd_io -v dd_io v v ol low level output voltage 0 - 0.1 * v dd_io v docid029656 rev 2 121/129 ST25R3911B electrical characteristics 123 3.4 electrical specifications v dd = 3.3 v, temperature 25 c unless noted otherwise. 3.3 v supply mode, regulated voltages set to 3.4 v, 27.12 mhz xtal connected to xto and xti. c l capacitive load - 0 - 50 pf r o output resistance - 0 250 550 ? r pd pull-down resistance pin miso pull-down can be enabled while miso output is in tristate. the activation is controlled by register setting. 51015k ? table 99. cmos outputs (continued) symbol parameter conditions min typ max unit table 100. electrical specifications symbol parameter min typ max unit comments i pd supply current in power-down mode 0.2 0.7 2 a register 00h set to 0fh (no clock on mcu_clk), register 01h set to 80h (3 v supply mode), register 02hset to 00h register 03h set to 08h, other registers in default state. i nfct supply current in initial nfc target mode 2.2 3.5 7 a register 00h set to 0fh (no clock on mcu_clk), register 01h set to 80h (3 v supply mode), register 02hset to 00h register 03h set to 80h (enable nfc target mode), other registers in default state. i wu supply current in wake- up mode 1.6 3.6 8 a register 00h set to 0fh (no clock on mcu_clk), register 01h set to 80h (3 v supply mode), register 02h set to 04h (enable wake-up mode), register 03hset to 08h, register 31h set to 08h (100 ms timeout, irq at every timeout), other registers in default state. i cs capacitive sensor supply current 0.6 1.1 2 ma register 00h set to 0fh (no clock on mcu_clk), register 01h set to 80h (3 v supply mode), register 02h set to 00h, analog test mode 14, other registers in default state. i rd supply current in ready mode 4.0 5.4 7.5 ma register 00h set to 0fh (no clock on mcu_clk), register 01h set to c0h (3 v supply mode, disable vsp_d), register 02h set to 80h, register 03h set to 08h, other registers in default state, short vsp_a and vsp_d. i al supply current, all active 6.2 8.7 12.5 ma register 00h set to 0fh, register 01h set to c0h (3 v supply mode, disable vsp_d), register 02h set to e8h (one channel rx, enable tx), register 03h set to 08h, register 0bh set to 00h, register 27h set to ffh (all rfo segments disabled), other registers in default state, short vsp_a and vsp_d. electrical characteristics ST25R3911B 122/129 docid029656 rev 2 i lp supply current, all active, low power receiver mode 4.8 6.8 10 ma register 00h set to 0fh, register 01h set to c0 h (3 v supply mode, disable vsp_d), register 02h set to e8h (one channel rx, enable tx), register 03 h set to 08, register 0b h set to 80 (low power mode), register 27h set to ffh (all rfo segments disabled), other registers in default state, short vsp_a and vsp_d. r rfo rfo1 and rfo2 driver output resistance 0.25 0.6 1.8 ? i rfo = 10 ma the following measurement procedure that cancels resistance of measurement setup is used: ? all driver segments are switched on, resistance is measured, ? all driver segments except the msb segment are switched on, resistance is measured, ? difference between the two measurements is resistance of msb segment, ? resistance of msb segment multiplied by two is the value of r rfo . z load load impedance across rfo1 and rfo2 81050 ? using load impedance lower than minimum value can result in permanent damage of the device v rfi rfi input sensitivity - 0.5 - mv rms f sub =848 khz, am channel with peak detector input stage selected. r rfi rfi input resistance 5 10 15 k ? - v por power on reset voltage 1.31 1.5 1.75 v - v agd agd voltage 1.4 1.5 1.6 v register 00h set to 0fh (no clock on mcu_clk), register 01h set to c0h (3 v supply mode, disable vsp_d), register 02h set to 80h, register 03h set to 08h, other registers in default state, short vsp_a and vsp_d. v reg regulated voltage 2.80 3.0 3.32 v manual regulator mode, regulated voltage set to 3.0 v, measured on pin vsp_rf: register 00h set to 0fh, register 01h set to 80h (3 v supply mode), register 02h set to e8h (one channel rx, enable tx), register 2a h set to d8 h . t osc oscillator start-up time 0.65 0.7 10 ms 13.56 mhz or 27.12 mhz crystal esr max = 150 ? max, load capacitance according to crystal specification, irq is issued once the oscillator frequency is stable. this parameter changes with esrmax parameter. table 100. electrical specifications (continued) symbol parameter min typ max unit comments docid029656 rev 2 123/129 ST25R3911B electrical characteristics 123 3.5 typical operating characteristics 3.5.1 thermal resistance and maximum power dissipation figure 31. t case vs. power with different copper area at t amb = 25c figure 32. r thca vs. copper area 7 f d v h y v 3 r z h u 4 ) 1 z l w k g l i i h u h q w f r s s h u d u h d 7 d p e ? & 3 r z h u ' l v v l s d w l r q > : @ 7 f d v h > ? & @ [ p p [ p p [ p p [ p p [ p p [ p p [ p p [ p p 0 6 y 9 0 6 y 9 5 w k b & $ > . : @ y v & r s s h u $ u h d 5 w k b & $ > . : @ $ u h d > f p @ package information ST25R3911B 124/129 docid029656 rev 2 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at www.st.com . ecopack ? is an st trademark. 4.1 qfn32 package information the ST25R3911B is available in a 32-pin qfn (5 mm x 5 mm) package (see figure 33 ). dimensions are detailed in table 101 . figure 33. qfn32 package outline 1. dimensioning and tolerances conform to asme y14.5m-1994. 2. co-planarity applies to the exposed heat slug as well as to the terminal. 3. radius on terminal is optional. 4. n is the total number of terminals. 5. this drawing is subjec t to change without notice. docid029656 rev 2 125/129 ST25R3911B package information 125 table 101. qfn32 5 mm x 5 mm dimensions (1) 1. all dimensions are in mm. all angles are in degrees. symbol (as specified in figure 33 ) min. typ. max. a 0.80 0.90 1.00 a1 0 0.02 0.05 a2 - 0.65 1.00 a3 - 0.20 - l 0.35 0.40 0.45 q0o-14o b 0.18 0.25 0.30 d - 5.00 (with bsc) - e - 5.00 (with bsc) - e - 0.50 (with bsc) - d2 3.40 3.50 3.60 e2 3.40 3.50 3.60 d1 - 4.75 (with bsc) - e1 - 4.75 (with bsc) - aaa - 0.15 - bbb - 0.10 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - fff - 0.10 - n (2) 2. total number of terminals. 32 part numbering ST25R3911B 126/129 docid029656 rev 2 5 part numbering note: parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st char ge. in no event, st wi ll be liable for any customer usage of these engineering samples in production. st quality has to be contacted prior to any decision to use these engineering samples to run qualification activity. table 102. ordering information scheme example: st25 r 39 11b - a qf t device type st25 = nfc/rfid tags and readers product type r = reader frequency range 39 = hf products product feature 11b = high performance hf reader / nfc initiator with 1.4 w supporting vhbr and aat temperature range a = -40 c to 125 c package/packaging qf = 32-pin qfn (5 mm x 5 mm) tape and reel t = 4000 pcs/reel docid029656 rev 2 127/129 ST25R3911B part numbering 128 table 103. ordering information scheme (unsawn wafer) (1) 1. for all information concerning the ST25R3911B delivered in unsawn wafer contact your nearest st sales office. example: st25 r 39 11b - a sw b device type st25 = nfc/rfid tags and readers product type r = reader frequency range 39 = hf products product feature 11b = high performance hf reader / nfc initiator with 1.4 w supporting vhbr and aat temperature range a = -40 c to 125 c delivery form sw = sorted wafer delivery medium b = wafer box revision history ST25R3911B 128/129 docid029656 rev 2 6 revision history table 104. document revision history date revision changes 26-sept-2016 1 initial release. 16-dec-2016 2 updated document title and image on cover page. updated features and description . updated section 1: functional overview , section 1.1.1: transmitter , section 1.1.2: receiver , section 1.1.3: phase and amplitude detector , section 1.1.5: capacitive sensor , section 1.1.7: quartz crystal oscillator , section 1.1.8: power supply regulators , section 1.1.9: por and bias , section 1.1.10: rc oscillator and wake-up timer , section 1.2.2: transmitter , demodulation stage , filtering and gain stages , digitizing stage , squelch , receiver in nfcip-1 active communication mode , section 1.2.4: capacitive sensor , section 1.2.5: wake-up mode , auto- averaging , section 1.2.8: a/d converter , section 1.2.12: communication with an external microcontroller and section 4.1: qfn32 package information . added section 1.2.13: direct commands . updated table 11: register preset bits , table 17: registers map . table 18: io configuration register 1 , table 21: mode definition register , table 28: iso14443b settings register 1 , table 34: auxiliary definition register , table 36: receiver conf iguration register 2 , table 37: receiver conf iguration register 3 , table 42: general purpose and no-response timer control register , table 46: mask main interrupt register , table 47: mask timer and nfc interrupt register , table 48: mask error and wake-u p interrupt register , table 51: error and wake- up interrupt register , table 53: fifo status register 2 , table 54: collision display register , table 56: number of transmitted bytes register 2 , table 59: antenna calibr ation control register , table 64: rfo am modulated level definition register , table 65: rfo normal level definition register , table 66: external field detector threshold register , table 69: regulator voltage control register , table 70: regulator and timer display register , table 72: rssi display register , table 75: capacitive sensor control register , table 77: auxiliary display register , table 80: amplitude measurem ent configuration register , table 84: phase measurement configuration register , table 88: capacitance measurement configuration register , table 92: ic identity register , table 93: ST25R3911B pin definitions - qfn32 package , table 95: electrostatic discharge , table 100: electrical specifications , table 102: ordering information scheme and table 103: ordering information scheme (unsawn wafer) . removed footnote from table 30: minimum tr1 codings . updated figure 4 in section 1.2.3: receiver , figure 8 in section 1.2.11: power supply system , figures 10 to 18 in section 1.2.12: communication with an external microcontroller , figures 19 and 20 in nfc field on commands , figure 22 in setting up the ST25R3911B for iso 14443a anticollision , figure 24 in section 1.2.18: felica? reader mode and figure 26 in section 1.2.21: antenna tuning . updated figure 30: ST25R3911B qfn32 pinout(1) . updated titles of figure 33: qfn32 package outline and of table 101: qfn32 5 mm x 5 mm dimensions . docid029656 rev 2 129/129 ST25R3911B 129 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 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